D-Board (1 Of 2) Block Diagram - Panasonic TH-50PZ77U Service Manual

15.31. D-Board (1 of 2) Block Diagram

D
FORMAT CONVERTER, PLASMA AI PROCESSOR
IC9807
Q9803
P+3.3V
P+15V
+3.3V
IC9806
IC9809
P+5V
Q9801
P+2.5V
+5V
P+5V
+2.5V
TO P25 D25
P+15V
P+15V 1
IC9800
2
P+15V
Q9800
P+5V
P+5V 7 P+1.2V
P+5V 9
STB+5V
STB+5V 10
+1.2V
F_STB_ON 13
ECO_ON 15
SOS
PS_SOS 16
MAIN
PANEL_ON 17
ALL_OFF P_CTL
18
VAD
Vda_Low 20
IC9011
TO DG35 D3 STB+3.3V/RESET
R3134
IIC_CTL
IIC_CONT 1
R9127
IIC/INT
IIC/INT 2
SCLK2
IIC_CLK2 3
STB+5V
SDA2
IIC_DATA2 4
MUTE 4
DISPEN 6
P_STATUS
D9802
READY 7
P_SOS
ALARM 8
P_CTL
PANEL_STBY_ON 11 D9811
STB5V 12
D9804
RXD
RXD 14
P15V 15 IIC/INT
TXD
TXD 16
D9808
ECO ON 18
SCLK1
IIC_CLK1 19
SDA1
IIC_DATA1 20
PDB1
PDB1 21
PSLCT
PSLCT 22
PDB0
PDB0 23
PBUSY
PBUSY 25
PSTB
PSTB 26
ALL_OFF 27
F_STB_ON 29
D6 1 2 4 5 6 7 8 9 10 11 12 13 14 15 16
FOR
FACTORY USE
TH-50PZ77U
D-Board (1 of 2) Block Diagram
P+3.3V P+1.2V
IC9801
P+3.3V
P+1.5V
P+3.3V
P+1.5V
+1.5V
P+1.5V
PANEL POWER PART SOS DET
P+15V OVER VOLTAGE LED BLINKING
P+3.3V FAIL VOLTAGE LED BLINKING
P+5V FAIL VOLTAGE LED BLINKING
P+2.5V
R9217 R9218
P+2.5V
R9215
R9207
R9219
Q9051 Q9052
P+15V SOS DET
P+1.2V
R9203
P+1.2V
STB
Q9046
+3.3V
STB+3.3V
ON/OFF
IC9001
R9141
Q9044
6
EEPROM
STB+3.3V STB+3.3V
ON/OFF (64k)
+3.3V 3
RESET 1
P+3.3V
R9868
R9871
P+3.3V
IC9002
TEMP SENSOR
Q9805
D9807
R9869
R9870
Q9806
P+1.2V/+1.5V/+2.5V/+3.3V
ON/OFF
P+15V
17 18 19 21
2 TIMES
3 TIMES
5 TIMES
STB+3.3V
D9020 R9220 R9221
P+5V
R9205
69 P+5V SOS DET
R9206
R9222 IC9003
Q9053 Q9054
MCU
P+5V SOS DET
70 P+3.3V SOS DET
71 P+15V SOS DET
9 RESET
14 IIC/INT
IIC/INT
6
SCLK2
15 IIC_CTL
IIC_CTL
5
26 S CLOCK2
SDA2
SCLK2
27 S DATA2
SDA2
28 TXD
TXD
29 RXD
RXD
50 S CLOCK1
SCLK1
51 S DATA1
SDA1
1
SCLK2
X9000
6
SDA2
27MHz
10
OSC
12
Q9010
INV. 16 REMOTE
68 5 23 24 65 66 67 74 72
D5 1 2 4 5 6 7 9 10 11 12 14 15 16 17 18
TO DG5
99
P+2.5V
P+1.2V P+3.3V
IC9500
VIDEO SIGNAL PROCESSOR
P+2.5V P+3.3V
P+1.5V
E+ LVDS0
E- LVDS0
E+ LVDS1
E- LVDS1 RGB
E+ LVDS2
E- LVDS2
E+ LVDS3
E- LVDS3
E+ LVDS4 LVDS
E- LVDS4 RX
E+ LVDSCLK
E- LVDSCLK
TTL
O+ LVDSCLK PARALLE
DATA
O- LVDSCLK
HD
O+ LVDS0
SYNC
O- LVDS0
VD PROCESSOR
O+ LVDS1
O- LVDS1
O+ LVDS2
O- LVDS2
3
O+ LVDS3
STB+3.3V
O- LVDS3
O+ LVDS4
O- LVDS4
LVDS_DET
LVDS_DET
6 2 5 1
DATA CONTROL(U)
NCS 36 NCS
ASDIO 37 ASDIO DATA CONTROL(D)
DATA0 38 DATA0
DISCHARGE
DCLK 39 DCLK
CONTROL
DRV_MUTE 18 DRV_MUTE
DRIVER RESET 20 DRIVER RESET
IC9007
EEPROM(FPGA)
(1MB)
IIC
CONT
76 73
Q9401 INV
20 21 23 24 25 26 28 29 30 31
TH-50PZ77U
D-Board (1 of 2) Block Diagram
TH-50PZ77U
1
2
3
4
R 10bit 5
10bit
G 6
B 10bit
R 10bit
7
10bit
G
8
B 10bit
9
HD,VD HD,VD
10
HD,VD
HD,VD
11
BUS SW 12
13
14
SUS CONTROL 15
SCAN CONTROL 16
17
18
19
20
21
22