Dg-Board (1 Of 4) Block Diagram - Panasonic TH-50PZ77U Service Manual

15.13. DG-Board (1 of 4) Block Diagram

IC4501
EEPROM
SDA SCL WC VCC
EDID1
JK4501
5 6 7 8
HDMI1
SUB5V
HPDT
D4526 D4527
19
+5V
18
DDCG
17 DDC_SDA0
SDA
16
SCL
15
DDC_SCL0
N.C.
14
CEC
13 CLK-
CLK- Q4504
12
CLKG
INV.
11 CLK+
CLK+
10 D0-
D0-
9 HDMI_5V_DET1
D0G
8 D0+
D0+ Q4503
7 D1-
D1- HDMI1 +5V DET
6
D1G
5 D1+
D1+
4 D2-
Q4501
D2- HPD1
3
D2G HDMI1 RESET
2 D2+
D2+
1
HDMI_CEC
IC4500
EEPROM
SDA SCL WC VCC
JK4500 EDID2
5 6 7 8
HDMI2
SUB5V
HPDT D4524
19
+5V
18
D4525
DDCG
17
SDA
DDC_SCL1
16
SCL
15
DDC_SDA1
N.C.
14
CEC
13 CLK-
CLK-
12
CLKG
11 CLK+
CLK+
D0- Q4505 EDID_WP
10
D0-
9
INV.
D0G
D0+
8
D0+
7 D1-
HDMI_5V_DET3
D1-
6
D1G
5 D1+ Q4502
D1+
D2-
4 HDMI2 +5V DET
D2-
3
D2G
D2+
2 Q4500
HPD3
D2+
1
HDMI2 RESET
DG DIGITAL SIGNAL PROCESSOR
MICOM
HDMI INTERFACE
FULL HD
TH-50PZ77U
DG-Board (1 of 4) Block Diagram
IC4509 IC4508
SUB3.3V
DVDD 1.8V CVDD 1.8V
VIN 8 VIN 8
1 VOUT 1 VOUT
CONT 5 CONT 5
SUB3.3V
DVDD CVDD PVDD DVDDIO
AUDIO
INTERFACE
CLK- RXA_CN
112
CLK+ RXA_CP
113
D0- RXA_0N
115
TMDS DATA
D0+ RXA_0P
116 RECEIVER
D1- RXA_1N
AND
118
TMDS DECODER VIDEO
D1+ RXA_1P SWITCH
119
INTERFACE
D2- RXA_2N
121
D2+ RXA_2P
122
HDCP
CIPHER DECRYPTOR
CHROMA
DEM
COLOR
DETECT
3D/2D
COM
VPK
CLK- RXB_CN
128
CLK+ RXB_CP
129
D0- RXB_0N
131
TMDS DATA
D0+ RXB_0P
132
RECEIVER
D1- RXB_1N
AND
134
TMDS DECODER
D1+ RXB_1P
135
IC4510
D2- RXB_2N
137
D2+ RXB_2P
HDMI I/F RECEIVER
138
10bit A/D
HDCP
CIPHER DECRYPTOR
105 DDCA_SCL
106 DDCA_SDA
1 DDCB_SDA
144 DDCB_SCL
108 107 12 11
SDA1
SCL1
IC4504
SUB3.3V
EEPROM
5 SDA WC 7
6 SCL VCC 8
81
IC4506
SUB5V
AVR 3.3V
VIN 7
1 VOUT
TV_MAIN_ON_DELAY
CONT 5
X4500
66 65
AVDD TVDD
7493_XRST
RESET 21
XIRQ3
INT1 19
HDMI_INT2
INT2 20
SPDIF HDMI_SPDIF
2
(RX_SCK)
SCLK HDMI_BCLK
8
(RX_SD0)
I2SO HDMI_SDIN
3
(RX_WS)
LRCLK HDMI_LRCK
7
38
UV0-UV9
45
55
58
24
Y0-Y9
33
46
47 R0-R3
52
53
VI1VSYNC
VS 18
VI1HSYNC
HS 17
VI1ENB
DE 16
VI1CKOUT
DCLKIN 48
VI1CLK
LLC 51
LPF
MAIN_Y
10bit AIN6 MAIN_Y
99 Q4516
A/D
MATRIX
LPF
MAIN_PB
10bit AIN8 MAIN_PB
RGB
78 Q4515
A/D
LPF
MAIN_PR
YUV 10bit AIN4 MAIN_PR
94 Q4514
A/D
SOY SOY SOY
97 Q4517
VS_IN 62
HS_IN 63
IC8302
FRONT END PROCESSOR
(TERRESTRIAL RECEIVER)
(FE_TO_PEAKS) TDO 108
(SPC_TO_FE) TDI 109
JTAG
TRST 111
TCK 113
TMS 114
CHOCLK
IBD07 98
SUB3.3V
CHODATA
IBD06 95
VDDH
CHOVAL
VDDA IBDEN 94
CHOPSYNC
SUB1.2V
IBPCK 93
FE_IRQ
VDDL INT 106 RF_L
FE_XRST
NRST 56
RF_R
24 XO
X8300 IBMSDA 43
25 XI
IBMSCL 44
SDA2 118 SDA RF_AFT
SCL2 117 SCL
RF_V
FAT_P
IBAINP 32
C8327-C8331
FAT_N C8333,C8334
IBAINN 34 L8306,07,09
BAND FILTER
IBAGCIF 49
TH-50PZ77U
DG-Board (1 of 4) Block Diagram
TH-50PZ77U
1
2
3
4
TU8300
BT30V TUNER
SUB5V
BTL
11
BB
1
BV
9
V_SUPPLY
17
L_OUT
4
R_OUT
5
Q8302 SDA
12
Q8303 SCL
13
AFT
14
Q8301 VIDEO_OUT
16
IFD_OUT1
18
IFD_OUT2
19
IF_AGC
20