Sharp HT-M700H Service Manual page 70

HT-M700H
U1A VHiES6698FD-1: Decoder (ES6698FD) (2/3)
Pin No. Terminal Name
106 VREF
YUV1
107 COMP
YUV3
108 REST
YUV4
109 FDAC
YUV7
110 VDAC
YUV6
111 VD33_DA
112 VS33_DA
113 YDAC
YUV5
114 CDAC
YUV2
115 UDAC
YUV0
116 TWS
SEL_PLL2
117 TSD0
SEL_PLL0
118 TSD1
SEL_PLL1
119 VS33
120, 121* TSD2, TSD3
122 MCLK
123 TBCK
124 SPD_DOBM
SEL_PLL3
125 SPDIF_IN
126 VD33
127 VS33
128 WBLCLK
129 WBL
130* LG
131 IP2
132 IP1
133*-136* FLAG0-FLAG3
137 VSS
138 VDD
139 TEXI
140 TESTAD
141 SBAD
142 FEI
143 AVSS_AD
144 CEI
145 TEI
146 RFRP
147 AVDD3_AD
148 VREF21
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
Input/Output
Input Internal voltage reference to video DAC.
Output YUV pixel 1 output data.
Input Compensation input.
Output YUV pixel 3 output data.
Input DAC current adjustment resistor input.
Output YUV pixel 4 output data.
Output Video DAC output.
Output YUV pixel 7 output data.
Output Video DAC output.
Output YUV pixel 6 output data.
Input Power for I/O power supply for VDAC.
– Ground for I/O power supply for VDAC.
Output Video DAC output.
Output YUV pixel 5 output data.
Output Video DAC output.
Output YUV pixel 2 output data.
Output Video DAC output.
Output YUV pixel 0 output data.
Output Audio transmit frame sync output.
Input System and DSCK output clock frequency selection is made at the rising edge of RESET#.
The matrix below lists the available clock frequencues and their respective PLL bit set-
tings.
Strapped to VCC or ground via 4.7 kohms resistor; read only during reset.
Output Audio transmit serial data port 0.
Input System and DSCK output clock frequency selection is made at the rising edge of RESET#.
The matrix below lists the available clock frequencues and their respective PLL bit set-
tings.
Strapped to VCC or ground via 4.7 kohms resistor; read only during reset.
Output Audio transmit serial data port 1.
Input System and DSCK output clock frequency selection is made at the rising edge of RESET#.
The matrix below lists the available clock frequencues and their respective PLL bit set-
tings.
Strapped to VCC or ground via 4.7 kohms resistor; read only during reset.
– Ground for I/O power supply.
Output Audio transmit serial data port 2 and 3.
Input/Output Audio master clock for audio DAC.
Output Audio transmit bit clock.
Output S/PDIF output.
Input Clock source select. Strapped to VCC or ground via 4.7 kohms resistor; read only during
reset.
Input S/PDIF input; (5 V tolerant input).
Input I/O power supply.
– Ground for I/O power supply.
Output DVD-RAM wobble detector circuit clock source to preamp.
Output DVD-RAM wobble output.
Output DVD-RAM land/groove flag.
Input DVD-RAM header position index 2.
Input DVD-RAM header position index 1.
Output To minitor servo status.
– Ground for core power supply.
Input Core power supply.
Input High-speed tracking error input.
Input Test AD input.
Input Sub-beam addition input signal.
Input Focus input error signal.
– Analog ground for ADC block.
Input Center error input signal.
Input Tracking error input signal.
Input RF ripple/envelope input signal.
Input Analog power supply for ADC block.
Output 2.1 V reference voltage.
8 – 2
Function