Sony DVP-F5 Service Manual page 76

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Pin No. Pin Name
55 VCC
56 CKSW1
57 OCSW1
58 OCSW2
59 2CH_CS
60 VES_CS
61 48/44.1K
62 MAMUTE
63 WIDE
64 C
65 CS0X
66 CS1X
67 CS2X
68 CS3X
69 CS4X
70 CS5X
71 CPUCK
72 NMIX
73 HSTX
74 FRRSTIN
75 VSS
76 MD0
77 MD1
TE
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78 MD2
79 XWAIT
80 BGRNTX
81 BRQ
82 RD
83 WRH
84 NC
85 to 92 HD0 to HD7
93 to 100 HD8 to HD15
101 VSS
102 to 109 HA0 to HA7
110 VCC
110 to 118 HA8 to HA15
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I/O
−
Power supply
I Chuck sensor input
I Tray sensor input
I Tray sensor input
O Chip select signal output to DAC (2CH)
O Chip select signal output to VES DSP
O PLL FS control signal output
O Audio mute signal output
O WIDE select signal output
−
Capacitor (0.1uF) connect between ground
O External ROM chip select signal output (to EEPROM)
−
Not used
O Chip select signal output (for AV DEC)
O Chip select signal output (for AV DEC)
O Chip select signal output (for ARP)
O Not used
O CPU clock signal output
−
Not used (fixed at "H")
−
Not used (fixed at "H")
I Reset signal input from IF CON
−
Ground
I Input of mode select 0 (fixed at "I")
−
Ground
−
Ground
I Wait signal input
−
Test terminal (fixed at "H")
−
Test terminal (fixed at "L")
O Read enable signal output
O High byte write enable signal output (16 bit and 8 bit)
−
Not used
I/O Data bus D0 to D7 (16 bit only)
I/O Data bus D8 to D15 (16 bit), D0 to D7 (8 bit)
−
Ground
O Address bus A00 to A07
−
Power supply
O Address bus A08 to A15
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