Yamaha CDR-S1000 Service Manual page 33

A B C
SCHEMATIC DIAGRAM (MAIN P.C.B.)
1
2
CD-RW
DRIVE
3
4
CD-RW
DRIVE
5
P-E39/J35
N-9
ANALOG
(2)
6
7
8
P-E38/J34
N-4
PANEL (2)
9
IC3 : PST572CMT-R
System Reset
1 VCC
10
3 OUT
2 GND
D E F
The voltage value is measured during playback.
The waveform is measured while CD OPTICAL (1kHz) signal is recorded.
SRAM
5.1
0
5.1
@1
0
5.1
@2
5.1 5.1
~ 0
~
~ 5.1 5.1
5.1
~ 5.1
~ ~ 0.3
5.1
~ ~
~ 5.1
~
5.1
~ ~
~ 0
~
~ ~ 5.1
5.1
~ 0
~ ~ 2.3
2.5
~ ~
~ ~ 5.1
0
~ ~
0 ~ ~
~
~
~
~
~
SRAM
~
~
~
5.1
~ 0
~
~ 5.1 ~
5.1 ~
~
~ ~ ~
~
~ ~
~ ~ ~
~
~ ~
~ 5.1 ~
~ ~ ~
0 5.1
~
~ ~ 5.1
~ ~
~ ~
~ ~
0 ~
t
RESET
@5 - A
@5 - B
5.1 5.0
0
5.1
3.5
0 3.5
0
5.1
3.6
3.6
0
0
~
~
~
~
0
Point e Point r
CH 1 : Pin 3 of IC206 or Pin 1 of IC8 CH 1 : Pin 3 of IC8 or Pin 80 of IC209
CH 2 : Pin 8 of IC206 CH 2 : Pin 8 of IC8
V : 2V/div (CH 1) V : 2V/div (CH 1)
V : 2V/div (CH 2) V : 2V/div (CH 2)
DC, 1 : 1 probe, H : 10 µsec/div DC, 1 : 1 probe, H : 10 µsec/div
CH1 CH1
0V
0V
CH2 CH2
0V
0V
G H
0
0
2.5
4.9
2.4
2.5
2.5
0
ACDR
2.5
2.5
!8
0.2
0.2
0
0
5.1
0
0
0
0
5.1
5.1
5.1
5.1
5.0
4.0
5.1
4.1
!9 !6
5.1
5.1
5.1
5.1
0
@3
5.1 ~
1.3 ~
0 ~
2.5 ~
i
3.5 ~
5.1 ~
5.1 CPU ~
5.1 ~
5.1 ~
5.1 ~
5.1 0
5.1 ~
5.1 ~
0 ~
!0
5.1 ~
5.1 ~
@3
5.1 ~
0 ~
0 ~
5.1 5.1
Point t (Pin 14 of IC2) Point i (Pin 51 of IC5) Point o (Pin 13 of IC8)
V : 2V/div, H : 50 µsec/div
V : 2V/div, H : 50 nsec/div V : 2V/div, H : 50 nsec/div
DC, 1 : 1 probe DC, 1 : 1 probe DC, 1 : 1 probe
0V
0V 0V
I J K
5.1
0 0
2.5 DIR 0
0 0
0
5.1
0 0
0
o
0 2.5
0 2.4
e
r
0 0.2
4.6 4.6
0
-5.0 0
0 0
0.1 0.2
EEPROM
5.1
5.1
5.1 0
0
5.1
0 0
SRAM
~ 5.1
~ ~
~ ~
~ ~
~ ~
~ ~
~ ~
~ ~
~ ~
~ ~
~ ~
~ ~
~ ~
0 ~
Point !0 (Pin 27 of IC5 or Pin 5 of IC7)
Point !6 (Pin 22 of IC4 or Pin 59 of IC205)
V : 2V/div, H : 2 µsec/div
V : 2V/div, H : 5 µsec/div
DC, 1 : 1 probe
DC, 1 : 1 probe
0V 0V
L M N
CDR-S1000
Point @ 2 (Pin 111 of IC4)
V : 2V/div, H : 10 msec/div
DC, 1 : 1 probe
0V
Point !8 (Pin 62 of IC4 or Pin 63 of IC205)
V : 2V/div, H : 5 µsec/div
Point @ 3
DC, 1 : 1 probe
(Pin 40 of IC4, Pin 13 of IC5 or Pin 44 of IC209)
V : 2V/div, H : 5 msec/div
DC, 1 : 1 probe
0V
0V
Point !9 (Pin 21 of IC4 or Pin 62 of IC205)
V : 2V/div, H : 5 µsec/div
DC, 1 : 1 probe
Point @ 5 -A (VCC of IC3)
Point @ 5 -B (OUT of IC3)
V : 2V/div (VCC)
0V
V : 2V/div (OUT)
DC, 1 : 1 probe, H : 1 sec/div
VCC
0V
Point @1 (Pin 6 of IC1)
V : 2V/div, H : 10 msec/div
OUT
DC, 1 : 1 probe
0V
POWER ON POWER OFF
0V
IC1, 2 : LP621024DM-70LLQ
128K x 8 Bit Static RAM
VCC
A0
NC 1 32 VCC
GND
A16 2 31 A15
ROW 512 x 2048
A14
A14 3 30 CE2
DECODER MEMORY ARRAY
A12 WE
4 29
A15
A7 A13
5 28
A6 6 27 A8
A16
A5 7 26 A9
A4 8 25 A11 I/O1
A3 9 24 OE
INPUT DATA
A2 10 23 A10 COLUMN I/O
CIRCUIT
A1 11 22 CE1
I/O8
A0 12 21 I/O8
I/O1 13 20 I/O7
I/O2 14 19 I/O6
I/O3 15 18 I/O5
GND 16 17 I/O4
CE2
CE1
CONTROL
OE CIRCUIT
WE
IC7 : W24258S-70LE-EL10
32K x 8 Bit Static RAM
A14 1 28 VDD
CLK GEN PRECHARGE CKT
A12 2 27 WE
A7 3 26 A13
A12 2
A6 4 25 A8
A5 5 24 A9 A14 1
A4 6 23 A11
A2 8
A3 OE
7 22
A2 A10 A3
8 21 7
CORE CELL ARRAY
A1 9 20 CS
A4 512 ROWS
6
A0 10 19 I/O8
64 x 8 COLUMNS
I/O1 11 18 I/O7 A5
5
I/O2 12 17 I/O6
A6 4
I/O3 13 16 I/O5
VSS 14 15 I/O4 A7 3
A13 26
I/O1 11 I/O CKT
DATA
CNTRL
I/O8 COLUMN DECODER
19
CLK
GEN
WE
27
CS 20
OE 22
23 21 9 10 25 24
IC6 : 24LC02BT
Electrically Erasable PROM
WP
7
HV GENERATOR
SDA 5
EEPROM
I/O MEMORY
ARRAY
CONTROL CONTROL XDEC
SCL 6
PAGE・LATCH
VSS 4
YDEC
VCC 8
SENSE
AMPLIFIER
N. C. R/W CONTROL
1 2 3
* All voltage are measured with a 10M Ω /V DC electric volt meter.
* Components having special characteristics are marked Z and
must be replaced with parts having specifications equal to those
originally installed.
* Schematic diagram is subject to change without notice.
E-36/J-32