Cpu 1/7 (Dmi, Peg, Fdi) - Clevo W240HU Series Service Manual

CPU 1/7 (DMI, PEG, FDI)

CAD N OTE: DP _COMPIO and I COMPO s ignals
shoul d be sh orted n ear ba lls and routed with
- typ ical im pedance < 25 mohms
1 .05 V S _ V T T 1 . 0 5V S _ V TT
R 3 89 R 3 9 0
1 K _ 0 4 24 .9 _ 1 %_ 0 4
EDP Function Disable
EDP_HPD: Pull-up10K- DISABLED
DP Compensation Signal
P Q 4 7
G
* MT N7 0 0 2 Z H S 3
[1 1] E MB _ H P D [1 1] DP _ A U XP
[1 1] DP _ A U XN
R3 8 8
*1 0 0 K _ 04
[1 1] DP _ T X P 0
[1 1] DP _ T X P 1
[1 1] DP _ T X P 2
[1 1] DP _ T X P 3
[1 1] DP _ T X N0
[1 1] DP _ T X N1
[1 1] DP _ T X N2
[1 1] DP _ T X N3
11/03
Sandy Bridge Processor 1/7
( DMI,PEG,FDI )
U 3 4A
P E G_ IC OM P I
P E G_ I CO MP O
B 2 7
[ 15 ] D MI_ T X N 0 D MI_ RX # [0 ] P E G _R CO MP O
B 2 5
[ 15 ] D MI_ T X N 1
A 2 5 D MI_ RX # [1 ]
[ 15 ] D MI_ T X N 2 D MI_ RX # [2 ]
B 2 4
[ 15 ] D MI_ T X N 3
D MI_ RX # [3 ] P E G_ R X # [ 0 ]
P E G_ R X # [ 1 ]
B 2 8
[ 15 ] D MI_ T X P 0 D MI_ RX [0 ] P E G_ R X # [ 2 ]
B 2 6
[ 15 ] D MI_ T X P 1 D MI_ RX [1 ] P E G_ R X # [ 3 ]
A 2 4
[ 15 ] D MI_ T X P 2 D MI_ RX [2 ] P E G_ R X # [ 4 ]
B 2 3
[ 15 ] D MI_ T X P 3
D MI_ RX [3 ] P E G_ R X # [ 5 ]
P E G_ R X # [ 6 ]
G2 1
[ 15 ] D MI_ R XN 0
E 2 2 D MI_ T X# [0 ] P E G_ R X # [ 7 ]
[ 15 ] D MI_ R XN 1 D MI_ T X# [1 ] P E G_ R X # [ 8 ]
F 2 1
[ 15 ] D MI_ R XN 2
D MI_ T X# [2 ] P E G_ R X # [ 9 ]
D 2 1
[ 15 ] D MI_ R XN 3 D MI_ T X# [3 ] P E G_ R X# [1 0 ]
P E G_ R X# [1 1 ]
G2 2
[ 15 ] D MI_ R XP 0
D 2 2 D MI_ T X[ 0] P E G_ R X# [1 2 ]
[ 15 ] D MI_ R XP 1 D MI_ T X[ 1] P E G_ R X# [1 3 ]
F 2 0
[ 15 ] D MI_ R XP 2
C 2 1 D MI_ T X[ 2] P E G_ R X# [1 4 ]
[ 15 ] D MI_ R XP 3 D MI_ T X[ 3] P E G_ R X# [1 5 ]
P E G_ RX [ 0 ]
P E G_ RX [ 1 ]
P E G_ RX [ 2 ]
A 2 1
[1 5 ] F D I_T X N 0 F D I0 _T X # [0 ] P E G_ RX [ 3 ]
H 1 9
[1 5 ] F D I_T X N 1
E 1 9 F D I0 _T X # [1 ] P E G_ RX [ 4 ]
[1 5 ] F D I_T X N 2 F D I0 _T X # [2 ] P E G_ RX [ 5 ]
F 1 8
[1 5 ] F D I_T X N 3
B 2 1 F D I0 _T X # [3 ] P E G_ RX [ 6 ]
[1 5 ] F D I_T X N 4 F D I1 _T X # [0 ] P E G_ RX [ 7 ]
C 2 0
[1 5 ] F D I_T X N 5
F D I1 _T X # [1 ] P E G_ RX [ 8 ]
D 1 8
[1 5 ] F D I_T X N 6 F D I1 _T X # [2 ] P E G_ RX [ 9 ]
E 1 7
[1 5 ] F D I_T X N 7 F D I1 _T X # [3 ] P E G_ R X [1 0 ]
P E G_ R X [1 1 ]
P E G_ R X [1 2 ]
A 2 2
[1 5 ] F D I_T X P 0
G1 9 F D I0 _T X [0 ] P E G_ R X [1 3 ]
[1 5 ] F D I_T X P 1 F D I0 _T X [1 ] P E G_ R X [1 4 ]
E 2 0
[1 5 ] F D I_T X P 2
F D I0 _T X [2 ] P E G_ R X [1 5 ]
G1 8
[1 5 ] F D I_T X P 3 F D I0 _T X [3 ]
B 2 0
[1 5 ] F D I_T X P 4 F D I1 _T X [0 ] P E G _ TX # [ 0 ]
C 1 9
[1 5 ] F D I_T X P 5 F D I1 _T X [1 ] P E G _ TX # [ 1 ]
D 1 9
[1 5 ] F D I_T X P 6 F D I1 _T X [2 ] P E G _ TX # [ 2 ]
F 1 7
[1 5 ] F D I_T X P 7
F D I1 _T X [3 ] P E G _ TX # [ 3 ]
P E G _ TX # [ 4 ]
J 1 8
[1 5 ] F D I_ F S Y NC 0
J 1 7 F D I0 _F S Y N C P E G _ TX # [ 5 ]
[1 5 ] F D I_ F S Y NC 1 F D I1 _F S Y N C P E G _ TX # [ 6 ]
P E G _ TX # [ 7 ]
H 2 0
[ 1 5 ] F DI _IN T F D I_ INT P E G _ TX # [ 8 ]
P E G _ TX # [ 9 ]
J 1 9
[1 5 ] F D I_ L S Y NC 0
H 1 7 F D I0 _L S Y N C P E G_ T X# [1 0 ]
[1 5 ] F D I_ L S Y NC 1 F D I1 _L S Y N C P E G_ T X# [1 1 ]
P E G_ T X# [1 2 ]
P E G_ T X# [1 3 ]
P E G_ T X# [1 4 ]
P E G_ T X# [1 5 ]
E DP _ C OM P A 1 8
e D P _ C OM P IO
A 1 7
B 1 6 e D P _ IC OM P O P E G _T X [ 0 ]
E DP _ H P D #
e D P _ H P D# P E G _T X [ 1 ]
P E G _T X [ 2 ]
P E G _T X [ 3 ]
D P _ A U X_ P C 1 5
C3 2 5 *0 . 1 u _1 0 V _ X 7R _ 04
D 1 5 e D P _ A U X P E G _T X [ 4 ]
C3 2 4 *0 . 1 u _1 0 V _ X 7R _ 04 D P _ A U X_ N
e D P _ A U X # P E G _T X [ 5 ]
P E G _T X [ 6 ]
P E G _T X [ 7 ]
C 1 7
C3 3 0 *0 . 1 u _1 0 V _ X 7R _ 04 D P _ T XP _0
e D P _ T X [0 ] P E G _T X [ 8 ]
C3 2 9 *0 . 1 u _1 0 V _ X 7R _ 04 D P _ T XP _1 F 1 6
C 1 6 e D P _ T X [1 ] P E G _T X [ 9 ]
C3 2 7 *0 . 1 u _1 0 V _ X 7R _ 04 D P _ T XP _2
e D P _ T X [2 ] P E G _ TX [1 0 ]
D P _ T XP _3 G1 5
C5 4 0 *0 . 1 u _1 0 V _ X 7R _ 04
e D P _ T X [3 ] P E G _ TX [1 1 ]
P E G _ TX [1 2 ]
D P _ T XN _ 0 C 1 8
C3 3 1 *0 . 1 u _1 0 V _ X 7R _ 04
e D P _ T X # [0] P E G _ TX [1 3 ]
C3 2 8 *0 . 1 u _1 0 V _ X 7R _ 04 D P _ T XN _ 1 E 1 6
e D P _ T X # [1] P E G _ TX [1 4 ]
D P _ T XN _ 2 D 1 6
C3 2 6 *0 . 1 u _1 0 V _ X 7R _ 04
e D P _ T X # [2] P E G _ TX [1 5 ]
C5 4 1 *0 . 1 u _1 0 V _ X 7R _ 04 D P _ T XN _ 3 F 1 5
e D P _ T X # [3]
P Z 98 8 2 7- 36 4 B -0 1 F
1 .0 5V S _V TT
20 mil
J 2 2 P E G_ C OM P
R6 3 2 4 .9_ 1 % _ 04
J 2 1
H 2 2
K 3 3
M 3 5
L 3 4
J 3 5
J 3 2
H 3 4
H 3 1
G 3 3
G 3 0
SC70-5 & SC70-3 Co-lay
F 3 5 Q1 7
E 3 4 5 1
G N D N C
E 3 2 2
GN D
D 3 3
D 3 1 4 3
V C C V O
B 3 3
C 3 2
*T MP 2 0
3 .3 V
J 3 3
Q1 6
L 3 5 2 1
1: 2 (4 mi ls :8 mi ls )
V C C O UT
K 3 4
H 3 5
C 9 9
H 3 2 3 C 10 0
G 3 4 G N D
0 .1 u_ 1 0 V _ X7 R _0 4
G 3 1
0 .1 u _1 0 V _ X 7R _ 04
G 71 1 S T 9 U
F 3 3
F 3 0
E 3 5
E 3 3
F 3 2 9/20
PLACE NEAR U3
D 3 4
EVT
E 3 1
C 3 3
B 3 2
M 2 9
M 3 2
M 3 1
L 3 2
L 2 9
K 3 1
K 2 8
J 3 0
J 2 8
H 2 9
G 2 7
On Board CPU Thermal Sensor
E 2 9
F 2 7
D 2 8 3.3 V
F 2 6
E 2 5
M 2 8
M 3 3
C9 7
M 3 0
L 3 1
*0 .1 u_ 1 6 V _ Y 5 V _ 0 4
L 2 8
U 1 1
K 3 0 1 4
R 1 2 2 *1 0 m i l _ 0 4
V D D TH E R M
K 2 7 D +_ C P U 2 6
D + A L E R T
J 2 9
J 2 7 B
Q1 8
H 2 8
G 2 8 3 7
* 2N 3 9 04 D -_C P U
D - S D A T A
E 2 8 5 8
F 2 8 G N D S CL K
D 2 7
* W 8 3L 7 7 1 A W G
E 2 6
D 2 5
[3 ,8 , 11 ,1 3 , 1 4, 15 , 1 7 ,1 8, 1 9 ,2 0 ,22 ,2 3 ,2 6 ,28 ,3 0 ,3 1,3 3 ,3 4 ,3 5]
[3 ,5, 18 , 1 9 ,2 0, 3 4 ,3 6 ]
Schematic Diagrams
T H E RM _ V OL T [2 7 ]
1
Sheet 2 of 43
3
CPU 1/7
2
(DMI, PEG, FDI)
Analog Thermal Sensor
C RIT _ T E MP _ R E P # [1 8 ]
TS # _ D IMM 0_ 1 [9 ,1 0 ]
S M D _ C P U _ T HE R M [1 4 , 2 7 ]
S M C _ C P U _ T HE R M [1 4 , 2 7 ]
3.3 V
1 .05 V S _V T T
CPU 1/7 (DMI, PEG, FDI) B - 3