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GROUP 3, PORT B DATA
BADR3 + D hex
READ/WRITE
7
6
D7
D6
GROUP 3, PORT C DATA
BADR3 + E hex
READ/WRITE
7
6
C8
C7
CH4
CH3
GROUP 3 CONFIGURE
BADR3 + F hex
READ/WRITE
7
6
MS
M3
5.4.5 8254 Configuration & Data
COUNTER 1 DATA
BADR3 + 10 hex
READ/WRITE
7
6
D7
D6
The 82C54 counters 1 and 2 have been configured in hardware to produce a 32-bit
counter for use in interrupt generation. This register provides access to the lower 16
data bits. Since the interface to the 82C54 is only 8-bits wide, write counter data in
two bytes; low byte first, followed by the high byte.
COUNTER 2 DATA
BADR3 + 11 hex
READ/WRITE
7
6
D7
D6
The 82C54 counters 1 and 2 have been configured in hardware to produce a 32-bit
counter for use in interrupt generation. This register provides access to the upper 16
data bits. Since the interface to the 82C54 is only 8-bits wide, write counter data in
two bytes; low byte first, followed by the high byte.
5
4
D5
D4
5
4
C6
C5
CH2
CH1
5
4
M2
A
5
4
D5
D4
5
4
D5
D4
15
3
2
D3
D2
3
2
C4
C3
CL4
CL3
3
2
CH
M1
3
2
D3
D2
3
2
D3
D2
1
0
D1
D0
1
0
C2
C1
CL2
CL1
1
0
B
CL
1
0
D1
D0
1
0
D1
D0
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