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The PCI Controller, a PLX-9052, has four configuration, control, and status registers
(Table 5-1). They are described in the following section.
I/O Region
Function
BADR0
PCI memory-mapped configuration
registers
BADR1
PCI I/O-mapped config. registers
BADR2
N/A
BADR3
Digital I/O registers
5.1 BADR0
BADR0 is reserved for the PLX-9052 configuration registers. There is no reason to
access this region of I/O space.
5.2 BADR1
BADR1 is a 32 bit register for control and configuration of interrupts.
5.2.1 INTCSR Configure
BADR1 +4C hex
32:15
14
13
X
X
X
READ/WRITE
7
6
X
PCINT
Note: For applications requiring edge triggered interrupts (LEVEL/EDGE bit 8 = 1),
the user must configure the INTPOL bit for active high polarity (bit 1=1).
The INTCSR (Interrupt Control/Status Register) controls the interrupt features of the
PLX-9052 controller. As with all of the PLX-9052 registers, it is 32-bits in length.
Since the rest of the register have specific control functions, those bits must be
masked off in order to access the specific interrupt control functions listed below.
Table 5-1. I/O Region Register Operations
12
11
ISAMD
X
5
4
X
X
5 REGISTER MAPS
Operations
32-bit double word
32-bit double word
N/A
8-bit byte
10
9
INTCLR
X
3
2
X
INT
9
8
LEVEL/EDGE
1
0
INTPOL
INTE
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