Badr3; Group 0 8255 Configuration & Data - Omega Engineering DIGITAL INPUT/OUTPUT PCI-DIO96 User Manual

5.4 BADR3

BADR3 is an 8-bit data bus for reading, writing and control of the individual 82C55
chips and the 82C54. Refer to Table 5-2 for register offsets.
REGISTER
BADR3 + 0
BADR3 + 1
BADR3 + 2
BADR3 + 3
BADR3 + 4
BADR3 + 5
BADR3 + 6
BADR3 + 7
BADR3 + 8
BADR3 + 9
BADR3 + A
BADR3 + B
BADR3 + C
BADR3 + D
BADR3 + E
BADR3 + F
BADR3 + 10h
BADR3 + 11h
BADR3 + 12h
BADR3 + 13h
BADR3 + 14h
BADR3 + 15h
The 82C55 may be programmed to operate in Input/Ouput (mode 0), Strobed
Input/Ouput (mode 1) or Bi-Directional Bus (mode 2). The following information
describes mode 0 operation. Users needing information regarding other modes of
operation should refer to an Intel or Intersil 82C55 data sheet.
Upon power-up, an 82C55 is reset and defaults to the input mode. No further
programming is needed to use the 24 lines of an 82C55 as TTL inputs.
5.4.1 Group 0 8255 Configuration & Data
GROUP 0, PORT A DATA
BADR3 + 0
READ/WRITE
7 6
D7 D6
Table 5-2. BADR3 Registers
READ FUNCTION
Group 0 Port A Data
Group 0 Port B Data
Group 0 Port C Data
Group 0 Configure
Group 1 Port A Data
Group 1 Port B Data
Group 1 Port C Data
Group 1 Configure
Group 2 Port A Data
Group 2 Port B Data
Group 2 Port C Data
Group 2 Configure
Group 3 Port A Data
Group 3 Port B Data
Group 3 Port C Data
Group 3 Configure
Counter 1
Counter 2
N/A
Counter Configuration
Interrupt Control 1
Interrupt Control 2
5 4
D5 D4
11
WRITE FUNCTION
Group 0 Port A Data
Group 0 Port B Data
Group 0 Port Data
Group 0 Configure
Group 1 Port A Data
Group 1 Port B Data
Group 1 Port C Data
Group 1 Configure
Group 2 Port A Data
Group 2 Port B Data
Group 2 Port C Data
Group 2 Configure
Group 3 Port A Data
Group 3 Port B Data
Group 3 Port C Data
Group 3 Configure
Counter 1
Counter 2
N/A
Counter Configure
Interrupt Control 1
Interrupt Control 2
3 2
D3 D2
1 0
D1 D0