Sony AVD-C70ES Service Manual page 35

Pin No. Pin Name
61 PHREFI
62 PHREFO
63 ZDFL
64 DSAL
65 ZDFR
66 DSAR
67 VDDSD0
68 ZDFC
69 DSAC
70 ZDFLFE
71 DSALFE
72 VSDSD1
73 ZDFLS
74 DSALS
75 ZDFRS
76 DSARS
77 VDDSD1
78, 79 IOUT0, IOUT1
80 VSCB0
81, 82 IOUT2, IOUT3
83 VDCB0
84, 85 IOUT4, IOUT5
86 VSIOB0
87 IANCO
88 IFULL
89 IEMPTY
90 VDIOB0
91 IFRM
92 IOUTE
93 IBCK
94 VSCB1
95 IERR
96 IANCI
97 IPLAN
98 IHOLD
99 VDCB1
100 IVLD
101 to 105 IDIN0 to IDIN4
106 VSIOB1
107 to 109 IDIN5 to IDIN7
110 VDIOB1
111 to 114 WAD0 to WAD3
115 TESTI
116 VSCB2
117 to 120 WAD4 to WAD7
121 VDCB2
I/O
I Bit clock signal (2.8224 MHz) input terminal for DSD data output Not used. (Open)
O Bit clock signal (2.8224 MHz) output to the digital audio processor
O Front L-ch Zero data flag detection signal output terminal Not used. (Open)
O Front L-ch DSD data output to the digital audio processor
O Front R-ch Zero data flag detection signal output terminal Not used. (Open)
O Front R-ch DSD data output to the digital audio processor
— Power supply terminal (+3.3 V) (for DSD data output)
O Center zero data flag detection signal output terminal Not used. (Open)
O Center DSD data output to the digital audio processor
O Woofer zero data flag detection signal output terminal Not used. (Open)
O Woofer DSD data output to the digital audio processor
— Ground terminal (for DSD data output)
O Rear L-ch zero data flag detection signal output terminal Not used. (Open)
O Rear L-ch DSD data output to the digital audio processor
O Rear R-ch zero data flag detection signal output terminal Not used. (Open)
O Rear R-ch DSD data output to the digital audio processor
— Power supply terminal (+3.3 V) (for DSD data output)
O Data output terminal for IEEE 1394 link chip interface Not used. (Open)
— Ground terminal (for core)
O Data output terminal for IEEE 1394 link chip interface Not used. (Open)
— Power supply terminal (+2.5 V) (for core)
O Data output terminal for IEEE 1394 link chip interface Not used. (Open)
— Ground terminal (for I/O)
Transmission information data output terminal for IEEE 1394 link chip interface
O
Not used. (Open)
Data transmission hold request signal input terminal for IEEE 1394 link chip interface
I
Not used. (Fixed at "L" in this set.)
High speed transmission request signal input terminal for IEEE 1394 link chip interface
I
Not used. (Fixed at "L" in this set.)
— Power supply terminal (+3.3 V) (for I/O)
Frame reference signal output terminal for IEEE 1394 link chip interface
O
Not used. (Open)
O Enable signal output terminal for IEEE 1394 link chip interface Not used. (Open)
Data transmission clock signal output terminal for IEEE 1394 link chip interface
O
Not used. (Open)
— Ground terminal (for core)
I Not used. (Fixed at "H" in this set.)
I Not used. (Fixed at "L" in this set.)
I Not used. (Fixed at "H" in this set.)
O Not used. (Open)
— Power supply terminal (+2.5 V) (for core)
I Not used. (Fixed at "H" in this set.)
I Not used. (Fixed at "H" in this set.)
— Ground terminal (for I/O)
I Not used. (Fixed at "L" in this set.)
— Power supply terminal (+3.3 V) (for I/O)
I External A/D data input terminal for PSP physical disc mark detection Not used. (Open)
I Input terminal for the test (normally: fixed at "L")
— Ground terminal (for core)
I External A/D data input terminal for PSP physical disc mark detection Not used. (Open)
— Power supply terminal (+2.5 V) (for core)
Pin Description
AVD-C70ES
35