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Philips Semiconductors
[1]
Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8000 acquisition points per equivalent fundamental
period. The calculation takes into account all harmonics and noise up to half clock frequency (NYQUIST frequency).
Conversion-to-noise ratio: S/N = EB
[2]
Output data acquisition is available after the maximum delay time t
timings are given for a 10 pF capacitive load. A higher load can be used but the timing must then be rechecked.
[3]
The input current must be limited in accordance with the limiting values.
2
[4]
The I
C-bus timings are given for a frequency of 100 kbit/s (100 kHz). This bus can be used at a frequency of 400 kbit/s (400 kHz).
CKADCO
DATA
R0 to R7, ROR
G0 to G7, GOR
B0 to B7, BOR
V in
Fig 11. Data timing diagram.
handbook, full pagewidth
V CCD
OE
output
data
t dLZ
output
data
LOW
f
= 100 kHz; switch S1 connected to V
OE
Fig 12. Timing diagram and test conditions of 3-state output delay time.
9397 750 07338
Product specification
Triple high-speed Analog-to-Digital Converter 110 Msps
6.02 + 1.76 dB.
t CPH
n
I n
I n
1
t d(s)
sample N
sample N
t dHZ
t dZL
HIGH
50%
10%
for t
and t
; switch S1 connected to GND for t
CCD
dLZ
dZL
Rev. 03 — 21 July 2000
, which is the time during which the data is available. All the
d(o)
t CPL
t d(o)
I n
I n
1
2
t h(o)
sample N
2
1
50%
t dZH
HIGH
90%
LOW
TDA8752B
OE
TDA8752B
50 % = 1.4 V
2.4 V
1.4 V
0.4 V
FCE475
50%
V CCD
S1
3.3 k
10 pF
FCE476
and t
.
dHZ
dZH
© Philips Electronics N.V. 2000. All rights reserved.
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