Components N2000, N2200 - Sony Ericsson K800 Electrical Repair Manual

N2000 ASIC Vincenne 2 A07 1.8V Cu-Plug Thin Ni (Pb Free Package)
ROP1013066/6
Pin Configuration Diagram
1 2 3 4 5
A
BOOST
SW VDD VBAT_ SW
ISENSE
BUCK BUCK C BOOST
-
B
BOOST
VSS V
VIBR ISENSE DACO1
BUCK BUCK
+
C
SIM VDD ONSW ONSW
IRQ
OFF _IO A B
D
CH CHSEN CHSEN BOOST
TEST
REG SE- SE+ FB+
E
Vbat-D
VSS_D V VSS
CHRG, DCIO
CHRG BOOST TH 4
SIM
F
SIM MOD_ VSS VSS
VBUS
VCC USB TH 30 TH 15
G
SIM SIM VSS_B VSS
DEC4
CLK RST SIM TH 14
H
SIM VSS
SDAT SRST DEC3
DAT TH 13
J
PCM VSS
PCMI SCLK AUXO2
CLK TH 27
K
PCM CLK_ VSS VSS
PCMO AUXI1N
SYN REQ BEAR CODEC
L VDD
LINE P BEARN AUXO1 DEC0 AUXI2P
LP
M
VDD VDD
XTAL1 LINE N BEARP AUXI1P
BEAR CODEC
View of Pin Configuration Diagram (as seen from top of package)
APPENDIX
6 7 8 9 10 11
ONSW VBAT_ DAC
LED1 VDD_ G VDD_B
C F CLK
PWR DAC B
LED2 VDD_F SCL
RST STR DATA
VSS_C
AD DAC EXT
BUCK SDA SLEEP
STR DAT LDO
DCDC
VSS VSS VSS PA
GPA13 SUB
TH 17 TH 18 TH 19 REG
VSS VSS VSS VSS PASEN
MOD1
TH 5 TH 6 TH 7 PA SE-
VSS VSS VSS FGSEN
FF_IN
TH 1 TH 8 TH 21 SE+
VSS VSS VSS VSS EXP DACO2/
TH 3 TH 2 TH 9 TH 22 OUT 4
VSS_A
VSS VSS VSS DIG
ANA- DACO3
TH 12 TH 11 TH 10 VSS
LOG
VSS VSS DIG
GPA12 GPA7 GPA6
TH 26 TH 25 VDD
VSS
AUXI3N MCLK GPA2 GPA4
ADC
AUXI2N MIC1N CCO GPA1 GPA3
VDD
VDD_IO
AUXI3P MIC1P ADC VDD_D
_18
Components N2000 - N2200
N2200 LDO 1.3V RYT1137810/1
Pin Configurations
TOP VIEW
8 7 6 5
12
VBAT_
A
LDOa,b
1 2 3 4
VDD_A
TDFN
2mm x 2mm
VDD
BUF
IOUT
Package Information
PASEN
SE+
FGSEN
SE-
VDD
PA/
DAC
IREF
VREF
GPA5
VDD_E
VBAT_
B
LDOd,e
COMMON DIMENSIONS
SYMBOL MIN. MAX.
A 0.70 0.80
D 1.90 2.10
E 1.90 2.10
A1 0.00 0.05
L 0.20 0.40
k 0.25 MIN.
A2 0.20 REF.
SEMC Electrical Repair Manual
Pin Description
8-PIN
NAME FUNCTION
TDFN
(2mm x 2mm)
Regulator Input. Supply voltage can range from +1.62V to +3.6V. Bypass IN
8 IN with at least a 1μF ceramic capacitor to GND (see the Capacitor Selection and
Regulator Stability section).
Ground. GND also functions as a heatsink. Solder to a large pad or circuit-
— GND
board ground plane to maximize SOT23 power dissipation.
5 GND Ground
Active-Low Shutdown Input. A logic-low reduces supply current to below 1μA.
SHDN
6
Connect to IN or logic-high for normal operation.
RESET rises
Open-Drain, Active-Low Reset Output.
RESET falls
100ms after the output has achieved regulation.
RESET
4
immediately if V drops below 82.5% of its nominal voltage, or if the
OUT
is shut down.
3 .C. Internally Connected. Leave floating or connect to GND.
Regulator Output. Sources up to 300mA. Bypass with a 4.7μF low-ESR
1 OUT
ceramic capacitor to GND.
2, 7 N.C. No Connection. Not internally connected.
Ground. EP also functions as a heatsink. Solder EP to a large pad or circuit-
— EP
board ground plane to maximize TDFN power dissipation.
1202-3085 rev. 2
K800 - K810
device
94 (121)