Circuit Description; Receiver Circuits; Rf Filter Circuit (Main Unit); 2Nd Mixer And If Circuits (Main Unit) - Icom IC-M700PRO Servise Manual

SECTION 3

3-1 RECEIVER CIRCUITS

3-1-1 RF FILTER CIRCUIT (MAIN UNIT)

Received signals from the antenna connector pass through
the transmit/receive switching relay (FILTER board RL4317)
and are then applied to the MAIN unit via J2.
The signals pass through the protection relay (RL2),
1.6 MHz cut off high-pass filter (L2–L4, C4–C8, C629) and
are then applied to one of nine bandpass filters (including
one low-pass filter for below 2.0 MHz). These filters are
selected by the filter control signals (B0–B8) as described
in the table below.
The filtered signals pass through the 30 MHz cut-off low-
pass filter (L71, L72, C130–C134, C618), and are then
applied to the 1st mixer circuit (Q6, Q7).
• RF FILTERS USED
Control Entrance
Frequency
signal coil
(MHz)
0.5–1.999 B0 L49
B1 L8
2–2.999
3–4.999 B2 L13
B3 L18
5–6.999
7–9.999 B4 L23
3-1-2 1ST MIXER AND IF CIRCUITS (MAIN UNIT)
The 1st mixer circuit converts the received signals into a
fixed frequency, 69.0115 MHz 1st IF signal using the PLL
output frequency. By changing the PLL frequency, only the
desired frequency is picked up at the pair of crystal filters
(FI1a, FI1b) at the next stage.
The IF amplifier (Q8) and resonator circuits are designed
between the filter pair. The PLL output signal (1LO) enters
the MAIN unit via J3 and is amplified at the 1st LO ampli-
fier (Q5) and then applied to the 1st mixer (Q6, Q7)
• RECEIVE FREQUENCY CONSTRUCTION
1st mixer
Q6, Q7
LPF or
BPF
0.5–29.999 MHz
1st LO:
69.5115–99.0115 MHz

CIRCUIT DESCRIPTION

Frequency Control Entrance
(MHz) signal coil
10–13.999 B5 L28
14–17.999 B6 L33
18–23.999 B7 L38
24–29.999 B8 L43
2nd mixer
Fl1a/Fl1b
D52
Crystal
filter
69.0115 MHz
2nd LO: 60.0 MHz

3-1-3 2ND MIXER AND IF CIRCUITS (MAIN UNIT)

The 1st IF signal from the crystal filter (FI1b) is converted
again into a 9.0115 MHz 2nd IF signal at the 2nd mixer
circuit (D52, L66, L67). The 60 MHz 2nd local signal (2LO)
from the PLL unit enters the MAIN unit via J4 to be applied
to the 2nd mixer.
The 2nd IF signal is passed through the noise blanker gate
(D15, D16) and amplified at the 2nd IF amplifier (Q16) and
then applied to one of the 9 MHz IF filters as described
below. The passed signal is amplified at the two stage 2nd
IF amplifiers (Q32, Q33) and is applied to a demodulator
circuit (D39 for H3E or IC10 for J3E and others).
• 2ND IF FILTERS USED
MODE
J3E, R3E, FSK
H3E
Optional narrow
FSK narrow,
A1A narrow
3-1-4 NOISE BLANKER CIRCUIT (MAIN UNIT)
The noise blanker circuit cuts off the IF circuit line at the
moment of receiving a pulse-type noise.
A portion of the 2nd IF signal between resonator circuits
(L83, L84 after stage of the 2nd mixer, D52) is amplified
at the noise amplifiers (Q9, IC8, Q11). The signal is then
detected at the noise detector (D17) to convert the noise
components to DC voltages.
The signals are then applied to the noise blanker switch
(Q13, Q14). At the moment the detected voltage exceeds
the Q13's threshold level, Q14 outputs a blanking signal
to close the noise blanker gate (D15, D16) by applying
reverse-biased voltage. Q15 turns the noise blanker circuit
ON and OFF.
H3E
Detector
Fl2 or
Crystal
filter
Other modes
9.0115 MHz
J3E, J2B, R3E, FSK:
FSK narrow, J2B narrow:
A1A:
3 - 1
Used filter Control signal
FI2 SEL8: low, H3E8: low
FI3/FI4 SEL8: low, H3E8: high
SEL8: high, H3E8: low
filter*
*Built-in to the GMDSS versions
D39
Audio output
Demodulator
IC10
BFO
9.013 MHz
9.0123 MHz
9.0116 MHz