LG MG810c Service Manual page 22

MG810C applies configuration #1 as its external memory interface, the external devices are connected
to as follow.
Table 4. External Device Spec. connected to memory interface
Calypso-Plus has NAND Flash interface and it allows NAND EEPROM as an mass external storage
facility. The interface implements a 8-bit parallel data bus in addition to the control signals for selecting
chip, writing/Reading, command and address latching, ready/busy status.
(MG810c does not use NAND I/F Ports of Calypso-Plus. NAND Memory is interfaced to MAP)
MG810C uses stacked memory MCP(pSRAM + NOR-Flash) as shown in (Figure 7.)
MEMORY 256Mb NOR & 128 Mb pSRAM
D(0:15)
V_FLASH
C399
0.1u
A(24)
Mirror bit only
U302
S71PL254JD0BFWTB0
D(0) J3
DQ0
D(1) G4
DQ1
D(2) K4
DQ2
D(3)
H5
DQ3
D(4) H6
DQ4
D(5) K7
DQ5
D(6)
G7
DQ6
D(7) J8
DQ7
D(8) K3
DQ8
D(9) H4
DQ9
D(10)
J4
DQ10
D(11) K5
DQ11
D(12) J7
DQ12
D(13)
H7
DQ13
D(14) K8
DQ14
D(15) H8
DQ15
J5
VCCF1
L5
VCCF2
J6
VCCS
C312
G3
0.1u
VSS1
J9
VSS2
A1
NC1
A10
NC2
M1
NC3
M10
NC4
B2
RFU1
B3
RFU2
B4
RFU3
B6
RFU4
B7
RFU5
B8
RFU6
B9
RFU7
C2
RFU8
C9
RFU9
F5
RFU10
R317
F6
RFU11
G5
NA RFU12
G6
RFU13
G8
RFU14
H9
RFU15
Figure 7. Memory interface scheme
3. H/W Circuit Description
G2 A(1)
A0
F2 A(2)
A1
E2 A(3)
A2
A(4)
D2
A3
F3 A(5)
A4
E3 A(6)
A5
A(7)
D3
A6
C3 A(8)
A7
C7 A(9)
A8
E7 A(10)
A9
A(11)
F7
A10
C8 A(12)
A11
D8 A(13)
A12
A(14)
E8
A13
F8 A(15)
A14
D9 A(16)
A15
G9 A(17)
A16
A(18)
F4
A17
E4 A(19)
A18
D7 A(20)
A19
A(21)
E6
A20
E9 A(22)
A21
F9 A(23)
A22
V_FLASH
K2
RFU16
K6
RFU17
K9
RFU18
L2
RFU19
L3
RFU20
L4
RFU21
L6
RFU22
L7
RFU23
L8
RFU24
L9
RFU25
H3
_OE
C6
_WE
C4
_LB
D4
_UB
H2
_CE1F
B5 R316 0
_CE2F
J2
_CE1S
D6
CE2S
E5
RY__BY
C5
WP_ACC
R318
D5
_RSTF
R319
- 21 -
A(1:23)
_RD
_WR
_BLE
_BHE
_CS5
_CS3
_CS1
_RDYMEM
FDP
0
TCXOEN
NA