Pioneer MJ-D707 Service Manual page 51

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PD5450A (IC104: CORE MAIN UNIT ASSY)
Mechanism Control m-com.
Pin Assignment (Top view)
TE
L 13942296513
Block Diagram
I/O PORT
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8 8
Port P0 Port P1
Internal Peripheral
A/D Converter
Functions
(10bits × 8 channels)
(expansion to 10 channels possible)
TIMER
Timer TA0 (16bits)
UART/clock-synchronized SI/O
Timer TA1 (16bits) (8bits × 2 channels)
Timer TA2 (16bits)
Timer TA3 (16bits)
CHC operation circuit
Timer TA4 (16bits)
(CCITT method)
Timer TB0 (16bits)
(formation polynomial: X
Timer TB1 (16bits)
Timer TB2 (16bits)
16 bits CPU CORE
Register
Monitoring timer
(16 bits)
R0H
R0H
R1H
R1H
R2
R2
DMAC (2 channels)
R3
R3
A0
A1
D/A Converter
FB
(8bits× 2 channels)
FB
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2 9
8
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3 6 7 1 3
8 8 8
Port P2 Port P3 Port P4
System clock generation
XCIN – XCOUT
16 12 5
+ X + X + 1)
MEMORY
Stack Pointer
R0L
R0L ISP
R1L
R1L USP
Vector Table
INTB
A0
A1
Analog Multiplier
.
MJ-D707, MJ-17D
9 4 2 8
1 5 0 5 8 2 9 9 4
8 8
Port P5 Port P6
XIN – XOUT
ROM
RAM
10k bite
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9 9
2 8 9 9
51