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IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS-41
Q8501 : SiI9135ACTU ( HDMI Receiver)-3/5
TERMINAL DESCRIPTION
Digital Video Output Pins
Pin Name Pin #
Q0 16
Q1 15
Q2 14
Q3 13
Q4 10
Q5 9
Q6 8
Q7 7
Q8 3
Q9 2
Q10 1
Q11 144
Q12 141
Q13 140
Q14 139
Q15 138
Q16 135
Q17 134
Q18 133
TE
L 13942296513
Q19 132
Q20 129
Q21 128
Q22 127
Q23 126
123
Q24
Q25 122
Q26 121
Q27 120
Q28 117
Q29 116
Q30 115
Q31 114
Q32 111
Q33 110
Q34 109
Q35 108
DE 19
HSYNC 20
VSYNC 21
EVNODD 22
ODCK 5
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Dir Description
Output 36-Bit Output Pixel Data Bus. Q35:0 is highly configurable using the
Output VDD_CONFIG register. It supports a wide array of output formats, including
Output multiple RBG and YCbCr bus formats. Using the appropriate bits in the PD
Output register, the output drivers can be put into a high impedance (tri-state) mode.
Output A weak, internal pull-down device brings each output to ground.
Output
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Output Data Enable.
Output Horizontal Sync Output.
Output Vertical Sync Output.
Output Indicates Even or Odd Field for Interlaced Formats.
Output Output Data Clock.
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