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IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS-23
Q8001 : FLI30502 (LCD TV Controller with Worldwide Standard Sound Processor
TERMINAL DESCRIPTION
Low bandwidth ADC input port
Pin Name
VDDA33_LBADC
LBADC_IN1
LBADC_IN2
LBADC_IN3
LBADC_IN4
LBADC_IN5
VSSA3_LBADC
RCLK PLL Pins
Pin Name
VBUFC_RPLL
VDD_RPLL_18
TE
L 13942296513
GND_RPLL_18
XTAL
TCLK
AVDD_RPLL_33
Digital video Input port
Pin Name
VID_CLK_1
VIDIN_HS
VIDIN_VS
VID_DATA_IN_0
VID_DATA_IN_1
VID_DATA_IN_2
VID_DATA_IN_3
VID_DATA_IN_4
VID_DATA_IN_5
VID_DATA_IN_6
VID_DATA_IN_7
VID_DATA_IN_8
VID_DATA_IN_9
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VID_DATA_IN_10
VID_DATA_IN_11
VID_DATA_IN_12
.
VID_DATA_IN_13
VID_DATA_IN_14
VID_DATA_IN_15

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Pin # I/O Description
1 AP Analog Powet (3.3V) for Low Bandwidth ADC Block. Must be bypassed with a 0.1 uF capacitor.
2 AI Low Bandwidth Analog input 1. The input signal connected to this pin, must be bypassed with a
0.1 uF capacitor and could be in the range of 0 to 3.3V. (peak to peak)
3 AI Low Bandwidth Analog input 2. The input signal connected to this pin, must be bypassed with a
0.1 uF capacitor and could be in the range of 0 to 3.3V. (peak to peak)
4 AI Low Bandwidth Analog input 3. The input signal connected to this pin, must be bypassed with a
0.1 uF capacitor and could be in the range of 0 to 3.3V. (peak to peak)
5 AI Low Bandwidth Analog input 4. The input signal connected to this pin, must be bypassed with a
0.1 uF capacitor and could be in the range of 0 to 3.3V. (peak to peak)
6 AI Low Bandwidth Analog input 5. The input signal connected to this pin, must be bypassed with a
0.1 uF capacitor and could be in the range of 0 to 3.3V. (peak to peak)
7 AG This pin provides the Return Path for LBADC inputs. Must be directly connected to the analog
system ground plane on board.
Pin # I/O Description
9 O Test Output. Leave this pin open. This reserved for factory testing purpose.
10 DP Digital power (1.8V) for ADC digital logic. Must be bypassed with capacitor to ground plane.
11 DG Digital GND for ADC clocking circuit. Must be directly connected to the digital system ground
plane.
12 AO Crystal oscillator output. Connect to external crystal.
13 AI Reference clock (TCLK) from the 19.6608 MHz crystal oscillator. Connect to external crystal
oscillator.
14 AP Analog Power (3.3V) for RCLK PLL. Must be byppased with a 0.1 uF capacitor.
Pin # I/O Description
151 I Video port data clock input meant for Video Input 1. Up to 135 MHz (Input, 5 V tolerant).
53 I When Video Input 1 is in BT656 mode, this pin acts as HSync Input for Video Input 2;
54 I When Video Input 1 is in BT656 mode, this pin acts as VSync Input for Video Input 2;
141
142
145 IO Input YUV data in 8-bit BT656 of Video Input 1
146 (Bidirectional, 5 V tolerant); or Y[0:7] in 16-bit format or Y/G[0:7] in 24-bit mormat
147
148
149
150
162
163
165 IO Input C [0:7] data in 16-bit fomat OR B/U in 24-bit format
166
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y
170
i
171
173
174
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