Block Diagram - Changer Unit (Cd Section (2/2)) - Sony XES-Z50 Service Manual

Q Q
3 7 6 3 1 5 1 5 0
7-7. BLOCK DIAGRAM – CHANGER UNIT (CD Section (2/2)) –
DATA, BCLK
1
(Page 84)
LRCK, WDCK
6
(Page 84)
GTOP,
RFCK, RAOF
2
(Page 84)
C16M
3
(Page 84)
CDRST
7
(Page 84)
T E
L 1 3 9 4 2 2 9 6 5 1 3
DATA, CLK
8
(Page 84)
WFCK, SCOR,
EXCK, SBSO
5
(Page 84)
05
w w w
.
D-RAM CONTROLLER
IC401
DIGITAL
OUT
DATA DATAI
10
DIGITAL
BCLK BCKI
D/A
9
SIGNAL
CONVERTER
SELECTOR
LRCK LRCI
PROCESSOR
11 INTERFACE
WDCK WDCI INTERFACE
13
D-RAM INTERFACE
TIMING
GTOP GTOP
8
GENERATOR
RFCK RFCK
7
READ/WRITE
RAOF XROI
BASE
6
COUNTER
C4M
DATA
5
LINKING
WFCK WFCK
3 CONTROL
SCOR SCOR
VWA
80
GRSRST A0 – A9
1
GRSCOR
79
ADDRESS
MONITOR
CPU INTERFACE
D1 – D4
2 XRST
61 62 64 74 60 58 59 63
25 46 28 24 26 22 23 27
SYSTEM CONTROLLER
IC301 (2/3)
4 47
38 39
6
5
TH301 TH302
EEPROM
IC302
x a o
y
i
– 85 –
http://www.xiaoyu163.com
8
D OUT
26
DATA DATA
24
BCK BCK
23
LRCK LRCK
25
CLOCK
XTAI BUFFER
GENERATOR
16
IC504
IC503
D-RAM
IC402
A0 – A9 D1 – D4
9 – 12, 14 – 18, 5 1, 2, 24, 25 23 4 3 22
ADDRESS BUS
DATA BUS
9 – 12, 14 – 18, 5 1, 2, 24, 25 23 4 3 22
A0 – A9 D1 – D4
XRAS RAS
Q Q
36
3 7 6 3
XCAS CAS
45
XWE WE1 D-RAM
37
IC403
XWE2 WE2
38
XOE OE1
46
XOE2 OE2
47
CD TEXT DECODER
IC303
SBSO
9 SSI
EXCK
8 SCLK
WFCK
77 WFCK
SCOR
76 SCOR
29 EXTAL
X302
10MHz
30 XTAL
CSO 49 6
CSI
50 7 CSO
CSI
CCLK 48 5 CCLK
REQ 45 4 REQ
BUSY 44 56 BUSY
D303
RSTO 43 28 RST
WE
RESET 30
BU. CHECK 64 78
BUCK
31 32
X301
8MHz
RESET SIGNAL
+5V GENERATOR
IC903
u 1 6 3
.
http://www.xiaoyu163.com
9 2 4 9 8
• Signal path.
: CD PLAY
DATA,
BCK, LRCK
9
(Page 87)
SYNC (44.1kHz)
10
(Page 87)
OE1
WE1
RAS
CAS
WE2
OE2
1 5 1 5 0 8 9 2 4
S-RAM
IC304
63 29 WE
22
CE 62 CE1
30 CE2
24 OE
+5V
BATTERY CHECK
11 (Page 93)
m
RST
12
(Page 93)
c o
– 86 –
XES-Z50
2 9 9
9 8 2 9 9