Sony XES-Z50 Service Manual page 114

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– DSP Board –
IC102, 202 HM51W4260CLTT-7
44 43 42 41 40 39 38 37 36 35
I/O BUS
256K MEMORY
ARRAY MAT
I/O BUFFER
SELECTOR
COLUMN DECODER
SELECTOR
COLUMN DECODER
I/O BUFFER
256K MEMORY
ARRAY MAT
I/O BUS
1 2 3 4 5 6 7 8 9 10
TE
L 13942296513
IC306 MM1284XFFE
1 SW 14
BUS ON OUT
BUS ON INPUT 2 13
SW
GND 3 12
BUS CLK 4 11
VREF
5
BUS DATA 6 10
9
RESET
7 8
BUS RESET
SW
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34 33 32 31 30 29 28 27 26 25
ADDRESS BUS
ROW
DECODER
I/O BUS AND
PERIPHERAL
CIRCUIT
I/O BUS AND
ROW
DECODER
ADDRESS BUS
11 12 13 14 15 16 17 18 19 20
IC401 MBM29F016-90PFTN-DSP02L
IC402 MBM29F016-90PFTN-DSP02H
VCC
1
BUS ON 2
LINK OFF
CLK OUT
3
4
5
DATA OUT
6
7
DATA IN
8
9
RESET
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
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8
IC302 AT24C32N-10SI-TR
START/
24 23
STOP
LOGIC
DEVICE
ADDRESS
COMPARATOR
A0 1
A1 2
A2
3
VSS 4
21 22
Q Q
3 6 7 1 3
NC
NC
A19
A18
X
A17
DECODER
A16
A15
A14
ADDRESS
A13
LATCH
Y
A12
DECODER
CE
STB
VCC
NC
RESET CONTROL
CIRCUIT
A11
A10
A9
A8
A7
A6
A5
A4
ERASE CIRCUIT
CHIP ENABLE/
NC
OUTPUT ENABLE
NC
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– 166 –
2 9 9 4 2 8
H.V.
EN
SERIAL
PUMP/
LOAD
CONTROL
TIMING
COMP
LOGIC
DATA
RECOVERY
DATA WORD X
R/W
EEPROM
ADDRESS/
DECODER
COUNTER
SERIAL
MUX
Y
DECODER
D OUT/
ACK
LOGIC
D IN
D OUT
1 5 0 5 8 2 9 9 4
16,777,216
CELL
MATRIX
Y GATE
I/O
BUFFER
DATA
LATCH
STB
LOW VCC
DETECTOR CIRCUIT
WRITE/ERASE
PULSE TIMER
WRITE CIRCUIT
m
CIRCUIT
co
9 9
8 VCC
7 WP
SCL
6
5
SDA
2 8 9 9
NC 48
NC 47
A20
46
NC 45
WE
44
OE
43
RY/BY
42
DQ7
41
DQ6
40
DQ5
39
DQ4
38
37
VCC
VSS 36
VSS 35
DQ3
34
DQ2
33
DQ1
32
DQ0
31
A0
30
A1
29
A2
28
A3
27
NC
26
NC 25