Sony XES-Z50 Service Manual page 71

QQ
3 7 63 1515 0
DSP BOARD IC301 HD6473048-DSP01 (MASTER CONTROLLER)
Pin No. Pin Name
1 VDD
2 PW-ON
3 S-OUT
4 S-CKO
5 DSPRST
6 2710-CE
7 EE-CKO
8 SP-CE
9 DSP-RDY
10 VPP
11 GND
12 S-OUT (TX)
13 UNISO
14 S-IN (RX)
TE
15 UNISI
L 13942296513
16 NIL
17 UNICKI
18
19
20
21
22 VSS
23
24
25
26
27
28
29 D10
30 D11
31 D12
32 D13
33 D14
34 D15
35 VDD
www
36
37
.
http://www.xiaoyu163.com
I/O
—
Power supply terminal (+5V)
Output of power on/off control signal for the system power supply (digital/analog power
O
supply, amp remote etc.) "H": power on
Serial data output to the EEPROM (IC302), input selector (IC415), digital signal processor
O
(IC601 CXD2710R), and electrical volume (IC1106, 1206, 1306)
Serial data transfer clock signal output to the input selector (IC415), digital signal processor
O
(IC601 CXD2710R), and electrical volume (IC1106, 1206, 1306)
Reset signal output to the digital signal processor (IC101, 201 CXD2711Q/IC601
O
CXD2710R), and digital filter (IC1101, 1201, 1301) "L": reset
O
Chip enable signal output to the digital signal processor (IC601 CXD2710R)
O Serial data transfer clock signal output to the EEPROM (IC302)
O
Chip enable signal output to the input selector (IC415)
Input of ready signal at data transfer from the digital signal processor (IC101, 201 CXD2711Q)
I
The start cause interruption occurs by a falling edge
I Not used (fixed at "L")
—
Ground terminal
UART (Universal Asynchronous Receiver/Transmitter) transmit output of the master bus
O
controller (CN12)
O
Serial data output to the bus interface (IC306) (for SONY bus)
UART (Universal Asynchronous Receiver/Transmitter) receive input of the master bus
I
controller (CN12)
I Serial data input from the bus interface (IC306) (for SONY bus)
I Not used (fixed at "L")
I
Serial data transfer clock signal input from the bus interface (IC306) (for SONY bus)
D0 I/O
D1 I/O
Two-way data bus with the flash memory (IC401)
D2 I/O
D3 I/O
—
Ground terminal
D4 I/O
D5 I/O
Two-way data bus with the flash memory (IC401)
D6 I/O
D7 I/O
D8 I/O
D9 I/O
I/O
I/O
Two-way data bus with the digital signal processor (IC101, 201 CXD2711Q) and flash
memory (IC402)
I/O
I/O
I/O
I/O
—
Power supply terminal (+5V)
Address signal output terminal In this set, the chip enable signal output to the digital signal
A0 O
processor (IC101 CXD2711Q)
x ao
y
Address signal output to the flash memory (IC401, 402), and chip enable signal output to the
A1 O
i
digital signal processor (IC201 CXD2711Q)
http://www.xiaoyu163.com
8
Q Q
3 6 7 1 3
u163
.
– 71 –
2 9 9 4 2 8
Function
1 5 0 5 8 2 9 9 4
m
co
9 9
2 8 9 9