Sony XES-Z50 Service Manual page 68

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DSP BOARD IC101 CXD2711Q (DIGITAL SIGNAL PROCESSOR FOR FRONT/REAR SPEAKER)
IC201 CXD2711Q (DIGITAL SIGNAL PROCESSOR FOR SUB-WOOFER SPEAKER)
Pin No. Pin Name I/O
1 VSS —
2 CRDY O
3 CCNT I
4 XCWR I
5 XCRD I
6 VDD —
7 CD0 I/O
8 CD1 I/O
9 CD2 I/O
10 CD3 I/O
11 VSS —
12 CD4 I/O
13 CD5 I/O
14 CD6 I/O
15 CD7 I/O
16 VDD —
17 MUTE I
18 CCS I
TE
L 13942296513
19 VSS —
20 MCKO O
21 VSS —
22 XTO O
23 XTI I
24 VSS —
25 (BIST) O
26 (TCK) O
27 (TDI) O
28 (TENA1) O
29 (TDO) O
30 (VST) I
31 VSS —
32 RESET I
33 BCLK O
34 LRCK I
35 BCK I
36 VSS —
37 SIA I
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38 SIB I
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Ground terminal
Output of ready signal at serial data transfer to the master controller (IC301)
The start cause interruption occurs by a falling edge
Input of control/data from address bus for the master controller (IC301) "L": data input
Strobe signal input for data writing from the master controller (IC301)
Data are written by a falling edge
Strobe signal input for data reading from the master controller (IC301) "L": data read
Power supply terminal (+3.3V)
Two-way data bus (LSB) with the master controller (IC301)
Two-way data bus with the master controller (IC301)
Ground terminal
Two-way data bus with the master controller (IC301)
Two-way data bus (MSB) with the master controller (IC301)
Power supply terminal (+3.3V)
Mute control signal input of the audio data "L": mute Not used (fixed at "H")
Input of chip select signal from address bus for the master controller (IC301)
Ground terminal
Master clock signal (18.432 MHz) output terminal Not used (open)
Ground terminal
System clock signal (33.8688 MHz) output terminal Not used (open)
System clock signal (33.8688 MHz) input terminal
Ground terminal
Output terminal for the test Not used (open)
Output terminal for the test Not used (open)
Output terminal for the test Not used (open)
Output terminal for the test Not used (open)
Output terminal for the test Not used (open)
Input terminal for the test Not used (fixed at "L")
Ground terminal
Reset signal input from the master controller (IC301) "L": reset
Block clock signal output terminal Not used (open)
L/R sampling clock signal (44.1 kHz) input of the serial in/out data
Bit clock signal (2.8224 MHz) input of the serial in/out data
Ground terminal
Serial audio data input terminal
IC101: Serial data (for front speaker) input from the CXD2710R (IC601)
IC201: Serial data (for sub-woofer speaker) input from the CXD2710R (IC601)
x Serial audio data input terminal ao u163
y
IC101: Serial data (for rear speaker) input from the CXD2710R (IC601)
IC201: Not used (fixed at "L")
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