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Prestigio Nobile 159W
Note: The flash bus doesn't have the highest performance until writing 00h to MZCFG register and
08h to SMZCFG register.
Memory Mapping
The host memory addresses are mapped into the following regions shown in the following table.
Some regions are always mapped and some are mapped only when the corresponding register is
active. And these regions may be mapped into the same range in the flash space
Features
Ø
Supports memory mapping between host domain and EC domain
Ø
Supports read/write/erase flash operations and locking mechanism
Ø
Supports two shared memory access paths: host and EC
Ø
Supports two flash contents protection: different access paths and different memory block
Ø
Supports timing control for memory device (flash)
1.2 Software Specification
A. System Memory
The System consists of DDR SDRAM memory on 64-bit bus and the size options are
8/16/32/64/128/256/512MB on each DIMM slot. The BIOS will automatically detect the amount of
memory during the POST. But the total RAM size can be used by user must be substrated by the size
of the video shared memory.
4.2
Enhanced IDE
The enhanced IDE specification has defined many data transfer modes as following:
1. PIO Mode 0, 1, 2, 3, 4
2. Multiword DMA Mode 0, 1, 2, 3, 4 ,5
3. Ultra DMA-33/66/100/133
4. Which transfer mode will be set depend on the used devices, core chip IDE interface
and BIOS supported. This model's BIOS support all the data transfer modes above,
and it will auto detect and initialize it during POST. The Ultra DMA-33/66/100/133 is
a new physical protocol used to transfer data between an Ultra DMA-33/66 capable
IDE controller and one or more Ultra DMA-33/66 capable IDE devices.
1-33
TECHNICAL SERVICE MANUAL
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