JVC KD-SX985 Service Manual page 41

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3 7 63 1515 0
LC75873NW(IC601):LCD Driver
1.Pin layout
60 41
61
80
1 20
3.Pin function
Pin No.
79,80
1,2,3
to 66
67
78
TE
L 13942296513
69
74
76
77
78
75
71
www
72
.
70
73
http://www.xiaoyu163.com
2.Block diagram
VDD1
VDD2
40
INH
21
OSC
VDD
VSS
Pin name
I/O
S1/P1 TO S4/P4
S5 to S68
O
COM1
COM2 O
COM3
I/O
OSC
I
CE
I
CL
I
DI
I
INH
VDD1
I
I
VDD2
x ao
y
i
VDD
-
VSS
-
http://www.xiaoyu163.com
8
COMON
DRIVER
CLOCK
GENERATOR
Description
Segment outouts for displaying the display data
transferred by serial data input.
The S1/P1 to S4/P4 pins can be used as general-
purpose output ports under serial data control.
Common driver outputs.
The frame frequency f0 is given by : Q Q
3 6 7 1 3
f0 = (FOSC/384)Hz.
Oscillator connection
An oscillator circuit is formed by connecting an
external resistor and capacitor to this pin.
Serial data transfer inputs.
Connected to the controller.
CE:Chip enable
CL:Synchronization clock
DI:Transfer data
Display off control input
INH= "L"(VSS) Display forced off
S1/P1 to S4/P4 = "L"
(These pins are forcibly set to the
segment output port function and held
at the low level.)
S5 to S68 = "L"
COM1 to COM3"L"
INH = "H"(HDD) Display on
However, serial data transfer is possible when
the display is forced off by this pin.
Used for applying the LCD drive 2/3 bias voltage
externally. Must be connected to VDD2 when a
1/2 bias drive scheme is used.
Used for applying the LCD drive 1/3 bias voltage
externally. Must be connected to VDD1 when a
u163
1/2 bias drive scheme is used.
Power supply connection. .
Provide a voltage of between 3.0 and 6.0V.
Power supply connection. Connect to ground.
2 9 9 4 2 8
SEGMENT DRIVER
SHIFT REGISTOR
ADDRESS
DETECTOR
1 5 0 5 8 2 9 9 4
m
co
KD-SX985
9 9
2 8 9 9
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