JVC KD-SX985 Service Manual page 26

KD-SX985
QQ
3 7 63 1515 0
TC94A14FA (IC621) : DSP & DAC
1.Terminal layout & block daiagram
48 47
49
50
51
LPF
52
53
54
55
56
57
58
59
TE 60
L 13942296513
61
Micro-
62
controller
interface
63
64
1 2
2.Pin function
Pin
Symbol I/O
No
1 BCK O
2 LRCK O
3 AOUT O
4 DOUT O
5 IPF O
6 V -
DD3
7 V -
SS3
8 SBOK O
www
9 CLCK O
10 DATA O
11 SFSY O
12 SBSY O
13 HSO I/O
14 UHSO
15 PV -
DD3
1-26
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46 45 44 43 42
Clock
generator
1-bit
DAC
Address
circuit
16 k
RAM
Audio out Digital
circuit output
3 4 5 6 7
Bit clock output pin.32fs,48fs,or 64fs selectable by command.
L/R channel clock output pin."L" for L channel and "H" for R channel. Output polarity
can be inverted by command.
Audio data output pin. MSB-first or LSB-first selectable by command.
Digital data output pin.Outputs up to double-speed playback.
Correction flag output pin. When set to "H", AOUT output cannot be corrected by C2
correction processing.
Digital 3.3V power supply voltage pin.
Digital GND pin.
Subcode Q data CRCC result output pin. "H" level when result is OK.
Subcode P-W data read I/O pin. I/O polarity selectable by command.
x ao
Subcode P-W data output pin.
y
Playback frame sync signal output pin.
Subcode block sync signal output pin. "H" level at S1 when subcode sync is detected. . i
General-purpose input / output pins.
Input port at reset.
PLL-only 3.3V power supply voltage pin.
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8
41 40 39 38 37
PWM
Servo
control
ROM
Digital equalizer
automatic
adjustment circuit
RAM
CLV servo
Synchronous
guarantee
Q Q
EFM
3 6 7 1 3
decoder
Sub code
decoder
8 9 10 11 12
Descroption
u163
.
2 9 9 4 2 8
36 35 34 33
32
31
D/A
30
29
A/D
28
27
26
25
24
Data
slicer
23
22
VCO 1 5 0 5 8 2 9
21
20
19
PLL
TMAX
18
17
13 14 15 16
m
co
9 9
9 4 2 8 9 9