EN 64
8.
8.6
Alignments 42" HD v4
1. Get Pattern to be Full White (jumper CN2012 on Logic Brd)
2. Check the waveform using an Oscilloscope.
•
Triggering through V_TOGG of LOGIC Board.
•
Connect the OUT 240 Test Point at the centre of
Y_buffer to other channel, and then check the first aid-
reset waveform from the last sustain of 1TV-Field.
•
Check the waveform as before by adjusting Horizontal
Division.
Check the Reset waveform when the V_TOGG Level
is changed.
•
Set the 15V by adjusting VR5002.
•
Set the 100V and 50us by adjusting VR5001
Figure 8-31 1st subfield from the last sustain within 1 frame
Figure 8-32 Rising ramp of aid-reset
Figure 8-33 Falling ramp of aid-reset
SDI PDP
Alignments
F_14991_023.eps
F_14991_024.eps
030805
F_14991_025.eps
030805
030805
VR5001 Adjustment : Risi
VR5002 Adjustment : Falling ramp(Yfr)
LJ92 - 01200A
Figure 8-34 Potmeter locations
1
2
3
Figure 8-35 DIP switch mode: Internal
1
2
3
Figure 8-36 DIP switch mode: External
ng ramp(Yrr)
F_14991_026.eps
160206
4
4