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DRX-1
Clock Circuit
ClockGen
PLL
regular clock
Raw clock
(CY2071)
slow-
(FPGA)
loopfilter
Fig. 13
The same can be applied for the audio clock. For this
clock, a frequency of 8.192 MHz, 11.2896 MHz or 12.228
MHz is required. This depends on the sample-rate
frequency(32kHZ, 44.1kHZ or 48kHZ)of the audio signal.
DV Decoder
The AV-data will go from the FIFO to the NW700. The
NW700 decodes the stream into video data in 656 format
and audio data in I2S format.
The microprocessor has the ability to read the status
registers of the NW700 through the FPGA. By reading
these registers, extra data from the DV stream, that is not
decoded into audio or video, can be sent to the digital
board using pin TXD of the serial interface. This data
includes time stamp and some more.
Audio & Video Output
The audio I2S data are sent to audio DAC UDA1334.
Analog audio left and right signals are connected to the
analog board.
The tristate buffer enables the digital video stream to the
Video Input Processor on the digital board when the DV
source is selected.
The clock delay synchronizes the AV clock with the AV
data at the output.
90
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