Table of Contents
Advertisement
A
B
DRX-1
1
SCHEMATIC DIAGRAM
ANALOG: FOLLOW ME
2950 A1
2954 D2
3950 A1
3954 B1
3958 C3
2951 B3
2955 D4
3951 A3
3955 C2
3959 D1
2952 D2
2956 E1
3952 B1
3956 C1
3960 D3
2953 D4
2957 E3
3953 B3
3957 C1
3961 E1
1
2
Follow Me
2
2950
100n
3950
A
4K7
7950-B
LM339D
3
3952
22K
3954
B
4K7
4
3956
C
2K2
I955
3957
2K2
7950-D
LM339D
5
D
I956
2952
2n2
I957
3959
2954
10M
180p
6
3965
E
I960
33K
I963
7
1
2
168
C
D
A, B, G model
3962 E2
3966 E4
7950 D4
I951 B2
I955 C1
I959 D3
3963 E3
7950 A2
7951 B2
I952 B2
I956 D1
I960 E1
3964 E3
7950 D2
7952 B3
I953 C2
I957 D1
I961 E3
3965 E2
7950 D2
F950 A3
I954 C3
I958 D3
I962 C2
3
4
FOME
5SW
I951
3953
15K
I952
2951
10u
I953
3958
4K7
7950-C
7950-A
LM339D
LM339D
I958
2953
2n2
I959
3960
2955
10M
180p
3966
33K
3
4
E
F
ANALOG: VPS
I963 E1
1990 D1
2992 A3
2995 C1
3991 C4
2990 A4
2993 B1
2996 D1
3992 B2
2991 A4
2994 C1
3990 C4
3993 D1
1
A
A
GNDV
B
B
7990
STV5348
5
I994
1
CVBS
SYNCHRONIZING
I995
2994
28
CBLK
DATA EXTRACTION
100n
C
C
GNDV
21
VCR_|TV
2995
I997
24
XTI
22p
2996
23
XTO
22p
I998
I999
25
VSSO
D
D
I988
3993
16
SCL
SCL1
100R
I989
3994
17
SDA
SDA1
100R
E
E
1
G
H
3994 E1
5991 A3
I988 D1
I991 C4
I994 B1
I997 C1
3995 E3
7990 B1
I989 D1
I992 C4
I995 C1
I998 D1
5990 A4
I987 E3
I990 B4
I993 B2
I996 C1
I999 D1
2
3
4
5SW
5SW
5991
GNDV
GNDV
GNDV
GNDV
GNDV
6
2
4
18
22
3
Data
DATA DECODING
CLAMPING
Clock
I991
DATA
DV_
19
PROCESSING
I992
20
TEST1
27
TEST2
8 PAGES
OSCILLATOR
MEMORY
FREQUENCY
BLAN
12
SYNTHETIZER
TIME BASE
R
8
DISPLAY
G
9
INTERFACE
I2C BUS
B
10
INTERFACE
Y
15
7
26
11
14
13
3995
GNDV
GNDV
10K
GNDV
2
3
4
I
J
VPS
A
GNDV
B
3990
47K
3991
C
47K
GNDV
D
E
Advertisement
Table of Contents
