Nikon coolpix L100 Repair Manual page 67

1-2. CP1 CIRCUIT DESCRIPTION
1. Circuit Description
1-1. Signal processor (SIG)
1. Signal preprocessing block
This block processes the raw data for the CCD.
2. Color synchronization block
This block color synchronizes the raw data and converts it to
YUV.
3. YUV processing block
This block carries out luminance correction and generates
the Y, Cu and Cv signals.
4. Zoom processing block
This block carries out processes such as zoom processing
for the Y, Cu and Cv signals.
1-2. BUF-A
After the data is received from signal processing (SIG), it is
converted into data arrays for each mode, and then a write
request to the SDRAM is output to the SDRAM control. The
BUF-A is further divided into the BUF-A1 block, BUF-A2 block
and BUF-A3 block.
1-3. BUF-D
The data is read from the SDRAM and converted to data ar-
rays for each mode and is then output to signal processing.
1-4. AE/AWB and AF calculation circuit (AEAF)
When the data is received from signal processing (SIG), evalu-
ation values are calculated for AF and for AE/AWB, and then
it is written to each of the 16 horizontal areas in the SDRAM
via the SDRAM control.
1-5. BUF-BC
The image data and the character data for the OSD (On
Screen Displays) are read from the SDRAM and displayed
on the monitor and the LCD.
1-6. SDRAM Ctrl
This controls the SDRAM access requests.
1-7. BUF-E/BUF-F and JPEG controller
This carries out compression and expansion of JPEG data
and outputs write and read requests to the SDRAM.
1-8. TGSG
The TG is the signal generator which drives the CCD (10
million pixels) and carries out drive mode control.
The SG is the signal generator which creates the reference
for the video sync signals.
2. Outline of Operation
When the shutter opens, the serial signals ("take a picture"
commands) from the 8-bit microprocessor is input to ASIC
(IC101) and operation starts. When the TG/SG drives the CCD,
picture data passes through the A/D and CDS, and is then
input to the ASIC as 12-bit digital signal. The AF, AE, AWB,
shutter, and AGC value are computed from this data, and
three exposures are made to obtain the optimum picture. The
data which has already been stored in the SDRAM is read by
the CPU and color generation is carried out. Each pixel is
interpolated from the surrounding data as being either R, G
and B primary color data to produce R, G and B data. At this
time, correction of the lens distortion which is a characteristic
of wide-angle lenses is carried out. After AWB and γ process-
ing are carried out, a matrix is generated and aperture cor-
rection is carried out for the Y, V and U signals, and the data
is then compressed by the JPEG method by (JPEG) and is
then written to card memory (SD card).
When the data is to be output to an external device, it is taken
data from the memory and output via the USB. When played
back on the LCD and monitor, data is transferred from memery
to the SDRAM, and the data elongated by JPEG decorder is
displayed over the SDRAM display area.
3. LCD Block
The LCD display circuit is located on the CP1 board, and
consists of components such as a power circuit.
The signals from the ASIC are 8-bit digital signals, that is
input to the LCD directly. The 8-bit digital signals are con-
verted to RGB signals inside the LCD driver circuit . This LCD
has a 3-wire serial, and functions such as the brightness and
image quality are controlled.
Because the LCD closes more as the difference in potential
between the VCOM (common polar voltage: AC) and the R,
G and B signals becomes greater, the display becomes darker;
if the difference in potential is smaller, the element opens and
the LCD become brighter.
In addition, the timing pulses for signals other than the video
signals are also input from the ASIC directory to the LCD.
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- E3 ･ L100 -
INC
VMA43007-R.3780.A