Figure B-11. Ai Sample Clk Timebase Signal Timing; Appendix B; Timing Signal Information - National Instruments Isolated Analog Input Device NI PXI-4224 User Manual

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AI SAMPLE CLK TIMEBASE Signal
PFI 0, PXI_Trig<0..5>, or PXI_Star can externally input the
AI SAMPLE CLK TIMEBASE signal, which is not available as an output
on the I/O connector. The onboard scan interval (SI) counter uses
AI SAMPLE CLK TIMEBASE as a clock to time the generation of the
AI SAMP CLK signal. Configure the pin you select as the source for
AI SAMPLE CLK TIMEBASE in level-detection mode. Configure
the polarity selection for the pin for either active high or active low.
The maximum allowed frequency is 20 MHz, with a minimum pulse width
of 23 ns high or low. There is no minimum frequency.
Either the 20 MHz or 100 kHz internal timebase generates
AI SAMPLE CLK TIMEBASE unless you select an external source.
Figure B-11 shows the timing requirements for
AI SAMPLE CLK TIMEBASE.
t
w

Figure B-11. AI SAMPLE CLK TIMEBASE Signal Timing

Appendix B

t
p
t
w
t = 50 ns minimum
p
t = 23 ns minimum
w
B-9

Timing Signal Information

NI PXI-4224 User Manual