Hdmi Board: Circuit Diagram - Philips HTS8100 Service Manual

Circuit Diagram and PWB Layout
HDMI Board: Circuit Diagram (Part 1)
1 2 3
P-scan_DeInterlacer
A
B 27M_CLK * 4106
22R
3152
1101
*
27M
10K
3153
*
* *
C
3174
27M_CLK
3103
* 22p 22R
7100
FLI2310
22R 2158
*
HSYNC 1
4102 HSYNC1_PORT1
VSYNC 2
VSYNC1_PORT1
4103
3175 3
FIELD_ID1_PORT1
27M_CLK 4
IN_CLK1_PORT1
D 5
22R HSYNC2_PORT1
6
VSYNC2_PORT1
* *
7
FIELD_ID2_PORT1
8
VDD1
9
VSS1
* 10
IN_CLK2_PORT1
11
B|Cb|D1_0
12
B|Cb|D1_1
13
B|Cb|D1_2
14
B|Cb|D1_3
*
15
B|Cb|D1_4
16
VDDcore1
17
VSScore1
18
B|Cb|D1_5
E 19
B|Cb|D1_6
20
B|Cb|D1_7
C(0) 21
R|Cr|CbCr_0
C(1) 22
R|Cr|CbCr_1
C(2) 23
R|Cr|CbCr_2
C(3) 24
R|Cr|Cb|Cr_3
C(4) 25
R|Cr|CbCr_4
C(5) 26
R|Cr|CbCr_5
C(6) 27
R|Cr|CbCr_6
C(7) 28
R|Cr|CbCr_7
YB(0)
29
G|Y|Y_0
30
VDD2
31
VSS2
YB(1)
32
G|Y|Y_1
YB(2)
F 33
G|Y|Y_2
YB(3)
34
G|Y|Y_3
YB(4) 35
G|Y|Y_4
36
VDDcore2
37
VSScore2
YB(5) 38
G|Y|Y_5
YB(6) 39
G|Y|Y_6
YB(7)
40
G|Y|Y_7
41
IN_SEL
42
TEST
43
DEV_ADDR1
P1 44
3107 22R DEV_ADDR0
P1 SCL_3V3 45
SCLK
3108 22R 46
SDA_3V3
P2
SDATA
3151 22R 47
G RESET
RESET_N
* 3168 47K 48
+3V3_D
VDD3
2153 100p 49
*
3109 47R VSS3
DATA(0) 50
3110 47R SDRAM_DATA_0
DATA(1) 51
3111 47R SDRAM_DATA_1
DATA(2) 52
SDRAM_DATA_2
*
+3V3_D
3105 10K
+1V8_CORE
+3V3_D
*
H
3106 10K
* Provision
I
1 2 3
3139 785 32540
4 5 6
DECOUPLING CAP FOR FLI2301 / FLI2310
+3V3_D
2108
100n
+3V3_DAC
2106 10u 16V
3100 3101 3102 2105
150R 27R
10R 100n
DAC
* 4107
+1V8_DAC +1V8_PLL
100n
2151
4 5 6
7. EN 55
7 8 9 10
+1V8_CORE
DECOUPLING CAP FOR FLI2301/ FLI2310
DECOUPLING CAP FOR FLI2301 / FLI2310
+1V8_PLL
+3V3_DAC
PLL DAC
PLL
DAC
156 ADD(0) P1
OE
P2,P4
155 47R 3154 YA(9) ADD(1) P1
G|Y|Y_OUT_7
154 P2,P4 47R 3155 YA(8) ADD(2) P1
G|Y|Y_OUT_6
153 P2,P4 47R 3156 YA(7) ADD(3) P1
G|Y|Y_OUT_5
P2,P4
152 47R 3157 YA(6) ADD(4) P1
G|Y|Y_OUT_4
P2,P4
151 47R 3165 YA(5) ADD(5) P1
G|Y|Y_OUT_3
P2,P4
150 47R 3166 YA(4) ADD(6) P1
G|Y|Y_OUT_2
149 P2,P4 47R 3179 YA(3) ADD(7) P1
G|Y|Y_OUT_1
P2,P4
148 47R 3180 YA(2) ADD(8) P1
G|Y|Y_OUT_0
147 ADD(9) P1
VSS8
146 ADD(10) P1
+3V3_D
VDD8
145 P2,P4 47R 3181 YA(1)
R|V|PR_OUT_7
P2,P4
144 47R 3182 YA(0) BA0 P1
R|V|PR_OUT_6
143 BA1 P1
R|V|PR_OUT_5
142
R|V|PR_OUT_4
141 SRAM_DQM
R|V|PR_OUT_3
140
R|V|PR_OUT_2
139
VSScore7 +1V8_CORE
*
138
VDDcore7
P2,P4
137 47R 3184 UVA(9)
R|V|PR_OUT_1
P2,P4
136 47R 3185 UVA(8) CLK P1
R|V|PR_OUT_0
P2,P4
135 47R 3186 UVA(7)
B|U|Pb_OUT_7
P2,P4
134 47R 3187 UVA(6) CSN P1
B|U|Pb_OUT_6
P2,P4
133 47R 3188 UVA(5) WEN P1
B|U|Pb_OUT_5
P2,P4 47R 3189 P1
132 UVA(4) CASN
B|U|Pb_OUT_4
P2,P4
131 47R 3196 UVA(3) RASN P1
B|U|Pb_OUT_3
P2,P4
130 47R 3197 UVA(2)
B|U|Pb_OUT_2
129
VSS7
128 +3V3_D
VDD7
P2,P4
127 47R 3198 UVA(1)
B|U|Pb_OUT_1
P2,P4
126 47R 3199 UVA(0)
B|U|Pb_OUT_0
P2,P4 47R 3183
125 P_CLK
CLKOUT
124
VSScore6 2150
*
123
VDDcore6 +1V8_CORE
122
CTLOUT4
10p
121
CTLOUT3
P2,P4 3169 22R
* RESET_SII
120
CTLOUT2
119 P2,P4 P_VSYNC
CTLOUT1
118 P2,P4 P_HSYNC
CTLOUT0
117
TEST_OUT1
116
TEST_OUT0
115
P1
TEST3
3177 22R
114
CLK
SDRAM_CLKIN
113
VSS6
112 P1
VDD6 +3V3_D
3178 22R
111
CLK P1
SDRAM_CLKOUT II0
110 SRAM_DQM
P1
SDRAM_DQM
109
CSN
SDRAM_CSN P1
108 BA0
SDRAM_BA0
P1
107
BA1
SDRAM_BA1
P1
106
CASN
SDRAM_CASN
P1
105
RASN
SDRAM_RASN
+3V3D_V
P1
WEN
AV3
7 8 9 10
11 12 13
+1V8_CORE
5100 F101
PLL
47u
4105
7103 5103
100n
LF18ABDT
2100
60R
* 2154 +1V8_DAC
F100 5101 F102
1 3
IN OUT 6.3V 47u
DAC +3V3_D
COM
47u
2104
2102
2103
+1V8_PLL
220n 5102 F103
AP1 47u
2107
AZ1
7101
MT48LC2M32B2P-5:G
VDD VDDQ
25
0
SDRAM
26
1
27
2
2M x 32
60
3
61
4 0
62
A
5
2k-1
63
6
64
7
65
8
66
9
24
10
3162 47R
22
0
3163 47R
23 BA
1
P1 16
0
71
1
DQM
28
10p
2
3173 22R *
59
3
2152
68
CLK
67
+3V3_MEM
CKE
20
CS
3160 47R
17
WE
3161 47R 18
CAS
3164 47R
19
RAS
14
21
30
57
NC
69
70
73
VSS VSSQ
+3V3D_V
*
1R0
3170
*
3172
1R0
3139-243-35752-130-a2-sh1.pdf 2007-03-05
11 12 13
14 1101 B3 3154 D9
2100 A12 3155 D9
2101 A5 3156 D9
2102 A12 3157 D9
2103 A12 3158 I7
2104 A13 3159 I7
2105 B6 3160 E10
2106 A5 3161 E11
2107 B12 3162 E10
+1V8_HDMI
2108 A6 3163 E11
2109 C5 3164 E10
A
2110 A7 3165 D9
2111 A6 3166 D9
2112 A6 3167 G10
2113 B8 3168 G1
2114 A5 3169 F8
2115 A5 3170 H10
2116 A6 3171 H10
2117 B8 3172 I10
2118 A5 3173 E10
2119 A6 3174 C2
2120 B8 3175 D1
2121 B8 3177 G8
B
2122 A8 3178 G8
2123 A8 3179 D9
2124 A8 3180 D9
2125 A8 3181 D9
2126 A9 3182 E9
2127 A9 3183 F8
2128 A9 3184 E9
2130 B12 3185 E9
2131 B12 3186 E9
2132 B12 3187 E9
2133 B13 3188 E9
C 2134 B10 3189 E9
+3V3_MEM
2135 B10 3190 D2
2136 B9 3191 D2
2137 B9 3192 D1
2138 A9 3196 E9
2139 B9 3197 F9
2140 B13 3198 F9
2141 B13 3199 F9
2142 C13 4100 H1
2 DATA(0)
0
2143 C13 4101 H1
4 DATA(1)
1
5 DATA(2) 2144 C13 4102 D1
2
7 DATA(3)
2145 C12 4103 D1
3
8 DATA(4) D
2146 C12 4105 A10
4
10 DATA(5)
5 2147 C13 4106 B3
11 DATA(6)
6
2148 B10 4107 B4
13 DATA(7)
7
74 DATA(8) 2149 B10 5100 A12
8
76 DATA(9) 2150 F9 5101 A12
9
77 DATA(10)
2151 C6 5102 B12
10
79 DATA(11)
11 2152 E11 5103 A13
80 DATA(12)
12
2153 G2 7100 C3
82 DATA(13)
13
83 DATA(14) 2154 A10 7101 C12
14
85 DATA(15)
2155 B12 7103 A11
15
D 31 DATA(16)
2156 C2 7121 G11
16
33 DATA(17)
17 2157 C3 7122 H11
34 DATA(18) E
18
2158 C2 F100 A11
36 DATA(19)
19
37 DATA(20) 2159 E1 F101 A12
20
39 DATA(21) 3100 B4 F102 A12
21
40 DATA(22)
3101 B5 F103 B12
22
42 DATA(23)
23
3102 B5
45
DATA(24)
24
3103 C1
47 DATA(25)
25
48 DATA(26) 3104 D1
26
50 DATA(27) 3105 H1
27
51
DATA(28)
28 3106 H1
53 DATA(29)
29 3107 G1
54 DATA(30)
30
56 3108 G1
DATA(31)
31
F 3109 G1
3110 G1
3111 G1
3112 I3
3113 I3
3114 I3
3115 I4
3116 I3
3117 I3
3118 I4
3119 I3
3120 I4
G
3121 I4
3122 I4
3123 I4
3124 I4
3125 I4
3126 I5
3127 I4
3128 I5
3129 I4
3130 I5
3131 I5
3132 I5
H
3133 I5
3134 I5
3135 I5
3136 I5
3137 I5
3138 I5
3139 I5
3140 I7
3141 I6
3142 I6
3143 I6
3144 I6
I
3145 I6
3146 I6
3147 I6
3148 I6
3149 I6
3150 C7
3151 G1
3152 B2
3153 B3
14