Akai LCT3201ad Service Manual page 58

5.3 LVDS DATA MAPPING
a. None-JEIDA normal Specification
RXCLK
RXIN0
RXIN1
RXIN2
RXIN3
PREVIOUS
b. JEIDA Specification
RXCLK
RXIN0 R3
RXIN1 G4
RXIN2 B5
RXIN3 R1
PREVIOUS
1CLK
R1 G0
R0
G2 G1 B1
B2 DENA
B3
R6
R7 Preserve
1CLK
R2 G2 R7
G3 B3 B2
B4
DENA VD
R0
Preserve B1
DATA for current CLK cycle
8bit LSB: R0,G0,B0
Parallel TTL Data Inputs Mapped to LVDS outputs
R5 R4 R3
B0 G5 G4
Hsync B5
Vsync
B6 G7
B7
DATA for current CLK cycle
R6 R5 R4
G7 G6 G5
B7 B6
HD
B0 G1 G0
57
R0
R2 R1
G3 G2 G1
B4 B3 B2
G6 R7 R6
R3 R2
G3
G4
B5 B4
R1 R0
NEXT
NEXT