Digital Outputs; Analog Outputs - Philips DVD963SA Service Manual

EN 90 9. DVD963SA
9.9.4 Diagram P1: FLI2301 (item 7100)
BLOCK DIAGRAM
Port 2
8-bit
Input Processor
656 Input
with Auto Sync
and auto Adjust
Port 1
8/16/24-bit
RGB/YCrCb
Input
Clock
Generation
PLLs
1
HSYNC1_PORT1
VSYNC1_PORT1
FIELD ID1_PORT1
IN_CLK1_PORT1
5
HSYNC2_PORT1
VSYNC2_PORT1
FIELD ID2_PORT1
VDD1
VSS
1 0
IN_CLK2_PORT1
B/Cb/D1_0
B/Cb/D1_1
B/Cb/D1_2
B/Cb/D1_3
1 5
B/Cb/D1_4
VDDcore1
VSScore
B/Cb/D1_5
B/Cb/D1_6
2 0
B/Cb/D1_7
R/Cr/Cb Cr_0
R/Cr/Cb Cr_1
R/Cr/Cb Cr_2
R/Cr/Cb Cr_3
2 5
R/Cr/Cb Cr_4
R/Cr/Cb Cr_5
R/Cr/Cb Cr_6
R/Cr/Cb Cr_7
G/Y/Y_0
VDD2 3 0
VSS
G/Y/Y_1
G/Y/Y_2
G/Y/Y_3
G/Y/Y_4 3 5
VDDcore2
VSScore
G/Y/Y_5
G/Y/Y_6
4 0
G/Y/Y_7
IN_SEL
TEST
DEV_ADDR1
DEV_ADDR0
SCLK 4 5
SDATA
RESET_N
VDD3
VSS
5 0
SDRAM DATA(0)
SDRAM DATA(1)
SDRAM DATA(2)
Circuit Descriptions and List of Abbreviations
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Simplified Internal Block Diagram
Noise Reducer,
Deinterlacer, Frame
Rate Converter and
SDRAM interface
2Mx32
SDRAM
(external)
Pin Diagram
Figure 9-18 FLI2301 (item 7100)
Output
Vertical and
Processor with
Horizontal
Sync Generation
Scalers
and DACs
Vertical and
Horizontal
Enhancers
16/20/24-bit
RBG/YCrCb

Digital Outputs

RBG/YCrCb

Analog Outputs

OE
1 5 5 G/Y/Y_OUT_7
G/Y/Y_OUT_6
G/Y/Y_OUT_5
G/Y/Y_OUT_4
G/Y/Y_OUT_3
1 5 0 G/Y/Y_OUT_2
G/Y/Y_OUT_1
G/Y/Y_OUT_0
VSS
VDD8
1 4 5 R/V/Pr_OUT_7
R/V/Pr_OUT_6
R/V/Pr_OUT_5
R/V/Pr_OUT_4
R/V/Pr_OUT_3
1 4 0 R/V/Pr_OUT_2
VSScore
VDDcore7
R/V/Pr_OUT_1
R/V/Pr_OUT_0
1 3 5 B/U/Pb_OUT_7
B/U/Pb_OUT_6
B/U/Pb_OUT_5
B/U/Pb_OUT_4
B/U/Pb_OUT_3
1 3 0
B/U/Pb_OUT_2
VSS
VDD7
B/U/Pb_OUT_1
B/U/Pb_OUT_0
1 2 5 CLKOUT
VSScore
VDDcore6
CTLOUT4
CTLOUT3
1 2 0 CTLOUT2
CTLOUT1
CTLOUT0
TEST OUT1
TEST OUT0
1 1 5
TEST3
SDRAM CLKIN
VSS
VDD6
SDRAM CLKOUT
1 1 0
SDRAM DQM
SDRAM CSN
SDRAM BA0
SDRAM BA1
SDRAM CASN
1 0 5
SDRAM RASN
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