Sharp CD-PC1881V Service Manual page 55

ICV3 VHiSDM4260C-1: DRAM (SDM4260C)
Port Name
Pin No.
1 VDD
2-10 DQ0-DQ7
11*,12* NC
13 WE
14 RAS
15* NC
16-19 A0-A3
20 VDD
21 VSS
22-26 A4-A8
27 OE
28,29 UCAS, LCAS
30* NC
31-34 DQ8-DQ11
35 VSS
36-39 DQ12-DQ15
40 VSS
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
RAS
14
29
LCAS
28
UCAS
13
WE
A0 16
A0-A8
17
A1
A2
18
19
A3
A4
22
23
A5
A0-A8
A6 24
A7
25
A8
26
Power supply
Data input/output
Not used
Read/write enable
Row address strobe
Not used
Address input (row/refresh: A0 to A3) (Column: A0 to A3)
Power supply
Ground
Address input (row/refresh: A4 to A8) (Column: A4 to A8)
Output enable
Column address strobe
Not used
Data input/output
Ground
Data input/output
Ground
Clock generating
circuit
Coidmn decoder
I/O control circuit
Memory cell array
Figure 55 BLOCK DIAGRAM OF IC
Function
Lowar
Upper
– 55 –
CD-PC1881V
Lower data
Input buffer
Lower data
Output buffer
Upper data
Input buffer
Upper data
Output buffer
1
VDD
20
40
35
VSS
21
2 DQ0
3 DQ1
10
DQ7
31 DQ8
32
DQ9
39
DQ15
27
OE