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QQ
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Pin No.
Pin Name
182
CD-LRCK
183
VSS
184
CD-BCK
185
CD-C2PO
190
PIO [10:0]
193
VDD
195
VSS
197
VDD
199
VSS
202 to 204 HADDR [2:0]
206
CS
207
R/W
208
RD
TE
L 13942296513
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I/O
I
Programmable polarity 16-bit word synchronization to the decoder
(right channel HIGH).
—
Ground for core logic and I/O signals.
I
CD bit clock. Decoder accept multiple BCK rates.
I
Asserted HIGH indicates a corrupted byte. Decoder keeps the previous valid picture
on-screen until the next valid picture is decoded.
I/O
Programmable I/O pins.
—
3.3-V supply voltage for core logic and I/O signals.
—
Ground for core logic and I/O signals.
—
3.3-V supply voltage for core logic and I/O signals.
—
Ground for core logic and I/O signals.
I
Host address bus. 3-bit address bus selects one of eight host interface registers.
I
Host chip select. Host asserts CS to select the decoder for a read or write operation.
The falling edge of this signal triggers the read of write operation.
I
Read/write strobe in M mode. Write strobe in I mode. Host asserts R/W LOW to select
write and LOW to select Read.
I
Read strobe in I mode. Must be held HIGH in M mode.
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2 9
8
Function
Q Q
3
6 7
1 3
1 5
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9 4
2 8
0 5
8
2 9
9 4
2 8
m
9 9
9 9
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