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• IC506 MPEG VIDEO/AUDIO DECODER, VIDEO SIGNAL PROCESSOR (CL8830-PD0) (VIDEO BOARD (2/2))
Pin No.
Pin Name
1
PIO [10:0]
2 to 4
HDATA [7:0]
5
VDD
6
HDATA [7:0]
7
VSS
8 to 11
HDATA [7:0]
12
VDD
13
RESET
14
VSS
15
WAIT
16
INT
17
VDD
19
VSS
TE
L 13942296513
27
VDD
29
VSS
36
VDD
38
VSS
40
VDD
42
VSS
47
VDD
49
VSS
52
PIO [10:0]
53, 54
MDATA [15:0]
55
VDD
56
MDATA [15:0]
57
VSS
58 to 60
MDATA [15:0]
61
VDD
62
MDATA [15:0]
63
VSS
64
MDATA [15:0]
65
VDD
66
MDATA [15:0]
67
VSS
68
MDATA [15:0]
www
69
VDD
70
MDATA [15:0]
71
VSS
.
72 to 74
MDATA [15:0]
75
VDD
56
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I/O
I/O
Programmable I/O pins.
I/O
8 bit bl-directional host data bus. Host writes data to the decoder Code FIFO via
HDATA [7:0]. MSB of the 32-bit word is written first. The host also reads and writes
the decoder internal registers and local SDRAM/ROM via HDATA [7:0].
—
3.3-V supply voltage for core logic and I/O signals.
I/O
8 bit bl-directional host data bus. Host writes data to the decoder Code FIFO via
HDATA [7:0]. MSB of the 32-bit word is written first. The host also reads and writes
the decoder internal registers and local SDRAM/ROM via HDATA [7:0].
—
Ground for core logic and I/O signals.
I/O
8 bit bl-directional host data bus. Host writes data to the decoder Code FIFO via
HDATA [7:0]. MSB of the 32-bit word is written first. The host also reads and writes
the decoder internal registers and local SDRAM/ROM via HDATA [7:0].
—
3.3-V supply voltage for core logic and I/O signals.
I
Hardware reset. An external device asserts RESET (active LOW) to execute a
decoder hardware reset. To ensure proper initialization after power in stable, assert
RESET for at least 20 Ms.
—
Ground for core logic and I/O signals.
O
Active LOW to indicate host initiated transfer is not complete. WAIT is asserted after
the falling edge of CS and reasserted when decoder is ready to complete transfer cycle.
Open drain signal, must be pulled-up to 3.3 volts. Driven high for 10 ns before tristate.
O
Host interrupt. Open drain signal, must be pulled-up to 3.3 volts. Driven high for
10 ns before tristate.
—
3.3-V supply voltage for core logic and I/O signals.
—
Ground for core logic and I/O signals.
—
3.3-V supply voltage for core logic and I/O signals.
—
Ground for core logic and I/O signals.
—
3.3-V supply voltage for core logic and I/O signals.
—
Ground for core logic and I/O signals.
—
3.3-V supply voltage for core logic and I/O signals.
—
Ground for core logic and I/O signals.
—
3.3-V supply voltage for core logic and I/O signals.
—
Ground for core logic and I/O signals.
I/O
Programmable I/O pins.
I/O
Memory address.
—
3.3-V supply voltage for core logic and I/O signals.
I/O
Memory address.
—
Ground for core logic and I/O signals.
I/O
Memory address.
—
3.3-V supply voltage for core logic and I/O signals.
I/O
Memory address.
—
Ground for core logic and I/O signals.
I/O
Memory address.
—
3.3-V supply voltage for core logic and I/O signals.
I/O
Memory address.
—
Ground for core logic and I/O signals.
I/O
Memory address.
—
3.3-V supply voltage for core logic and I/O signals.
x
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I/O
Memory address.
y
—
Ground for core logic and I/O signals.
i
I/O
Memory address.
—
3.3-V supply voltage for core logic and I/O signals.
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2 9
8
Function
Q Q
3
6 7
1 3
1 5
co
.
9 4
2 8
0 5
8
2 9
9 4
2 8
m
9 9
9 9
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