Schematic Diagram - Yamaha CDR-HD1500 Service Manual

A B
SCHEMATIC DIAGRAM (MAIN 1/2)
1
2
3
4
5
6
7
IC1: SN74LS06NSR IC4: PST572CMT-R
Inverter Buffer/Driver System Reset
1A 1 14 VCC
1 Vcc
1Y 2 6A
13
2A 3 12 6Y
3 Out
+
2Y 4 11 5A
3A 5 10 5Y
3Y 6 9 4A
2 Gnd
8
GND 7 8 4Y
9
C D E
CLOCK
2.6
0
2
1 2.5 2.5
3
5.1
2.5
5.1
0
2.5
2.5
2.6
0
2.4
5.1
0 1.7
1.1
5.1
0
5.1
0
5.1
2.5
0
0
0
0
2.6
2.5
2.5
2.6
2.5
2.5
2.5
0
0
2.3
2.6
5.1
5.1 1 2 0
0
-4.9
0
0
0.1 3 4 5.1
0 0.9
0 0
5.1 2.1
A
0 2.4
5.1 0.9
0 5.1
5.1 5.1
5.1 0
5.1 CPU 5.1
5.1 5.1
5.1 5.1
5.0 5.1
0 5.1
5.0 5.1
4.9 5.1
5.1 5.1
0 5.1
5.1 0
5.1 4.9
2.6 5.1
0 5.0
5.1
5.1 4.9
5.1 0
0 0.1
0 5.1
0 ~
5.1 3.8
IC5: MSM5118160F-60JSR1
1Mw x 16 bit DRAM
WE OE
IC7: GLT44016
13 29
DRAM
Timing
RAS 14
Generator
I/O
OE
Controller
LCAS 31
Output
UCAS 8 WE
30 I/O 8
Buffers
Controller
UCAS
DQ1~DQ8
Column
LCAS
Input
10 Address 10 Column Decoders
8 8
Buffers
Buffers
RAS
I/O
Internal
Sense Amplifiers 16 16
Refresh Selector
A0~A9
Address V
Control Clock CC
Counter
V
Input SS
8 8
Buffers
Row
Row
10 Address 10 Word Memory
Deco- DQ9~DQ16
Buffers Drivers Cells
ders
Output
8 8
Buffers
Vcc 21
A
0
On Chip
Vss Generator A
1
On Chip A
7
IVcc Generator
A
8
Vss 22
F G
~
1.3
5.1
0
5.1
~
0
~
4.9
0
B 0
ACDR ~
5.1
0
~
5.1
~
~
~
~
~
5.1
5.1
2.6
2.6
2.6
2.6
2.6
2.6
2.6
0
0
2.6
2.6
2.6
2.6
2.6
2.6
2.6
2.6
C
Ch 1
Ch 2
5.1 5 6 1 8
5.1 5.1 0.2 0.2 4.8
0
0.2 9 2 5.1
SYSTEM
RESET 5.1
5.1
14
5.1
11 10 11 10 3
5.1 0 5.1 5.1
5.1
14 5.1
0.2 6
5
5.1
7
0
5.1
0.2
13 12
FLASH MEMORY
5.1 0 5.1
12 13 8 9
1.6 2.0
2.3 5.1
3.0 0
5.1 0 1.7 0.9
1.7 0.9 1.3 1.4
1.9 2.4 1.4 2.4
1.9 2.1 1.7 1.3
1.8 0.9 2.4 2.1
5.1 0 1.6
1.8 1.3
0.9
1.6 1.2 4.9 1.8
1.3 1.4 5.1 5.1
1.4 2.6 1.3
1.8
0
3.4 1.2
4.8 3.4 2.3 1.9
1.4 0 3.8 1.4
1.7 2.6 1.9
2.4 2.5 2.6
2.2 2.6 2.5 1.7
2.3 2.5 2.5 4.9
2.7
2.4 2.5 0
2.7 2.5 2.4 5.1
5.1 0 2.3 2.2
DRAM
IC8: TC74HC14AF
Inverter
27 1A 1
13
1Y 2
28
2A 3
29
14
2Y 4
RAS CLOCK CAS CLOCK WE CLOCK OE CLOCK
GENERATOR GENERATOR GENERATOR GENERATOR
3A 5
1, 6, 20
21, 35, 40
3Y 6
Data I/O BUS 2 I/O1
3 I/O2 GND 7
COLUMN DECODERS
I/O3
4
REFRESH
SENSE AMPLIFIERS I/O4
5
COUNTER
I/O5
7
Y 0 - Y 8
8 I/O6
512 16
9
# All voltage are measured with a 10MΩ/V DC electric volt meter.
9 I/O7
I/O
16 10 I/O8 # Components having special characteristics are marked s and must be
BUFFER
17 . 31 I/O9
ROW
. . ADDRESS BUFFERS MEMORY
DECODERS 32 I/O10
AND PREDECODERS ARRAY
25
33 I/O11
26 X 0 - X 8 512 34 I/O12
# Schematic diagram is subject to change without notice.
I/O13
36
37 I/O14
38 I/O15
39 I/O16
H I
DRAM
5.1 0
5.1 ~
5.1 ~
5.1 ~
5.1 ~
5.1
5.1 2.2
5.1 ~
5.1 ~
5.1 2.2
5.1 2.5
5.1 5.1
~
5.1 ~
5.1 ~
5.1 ~
5.1 ~
5.1 0
ANALOG OUT
(DIGITAL)
4
0
IC11: MBM29F800BA-70PFTN
8Mbit Flash Memory
VCC
VSS
WE
BYTE
RESET
CE
OE
IC9: TC9246F-TEL
Clock Generator
VDD LOCK S2 S1 M2 M1 CKO VSS
VCC 16 15 14 13 12 11 10 9
14
13 6A
Lock µ-COM Interface
Detector
12 6Y
Programable Counter
11 5A VAR
10 5Y
Phase
VCO
Selector
Comparator
REF A0 to A18
9 4A
A-1
8 4Y
1 2 3 4 5 6 7 8
REF PD VDDA AMPI AMPO VSSA XI XO
replaced with parts having specifications equal to those originally
installed.
J K L
CDR-HD1500
Point Pin 74 of IC2
A
Point B Pin 129 of IC3
Point C VCC of IC4
and OUT of IC4
POWER ON
IC202: NJM2904M
Dual OP-Amp
V–
Q6
Q2 Q3 Q5
– Q1 Q4
Q7
INPUTS
OUTPUT
Q13
+
Q11
Q12
Q10
Q8 Q9
RY/BY DQ0 to DQ15
RY/BY
Buffer
Input/Output
Erase Voltage
Generator Buffers
State
Control
Command
Register
Program Voltage
Generator Chip Enable
STB
Data Latch
Output Enable
Logic
Y-Decoder Y-Gating
STB
Timer for
Address
Low Vcc Detector
Program/Erase
Latch
8,388,608
X-Decoder
Cell Matrix
45