Yamaha CDR-HD1500 Service Manual page 37

IC3 : YDC126-F (MAIN P.C.B.)
ACDR
No. Name I/O
97 RD1 I/O
98 RD0 I/O
99 VDD
100 RA12 O
101 RA11 O
102 RA10 O
103 RA9 O
104 RA8 O
105 RA7 O
106 VSS
107 RA6 O
108 RA5 O
109 RA4 O
110 RA3 O
111 RA2 O
112 RA1 O
113 RA0 O
114 VSS
115 /ROE O
116 /RWE O
117 /RAS O
118 /CAS O
119 MUTSP I
120 MUTAE I+
121 AVSS
122 PCO A
123 AVDD
124 /LOCK O
125 /TESTA I+
126 /TESTB I+
127 VSS
128 XI I$
129 XO O$
130 F256A O$
131 VDD
132 DINA I+
133 DINB I+
134 DINC I+
135 DOUT O
136 DDIN I
137 SI I+
138 SO O
139 /CSO O
140 SCK O$
141 DIRINT I+
142 UBIT I+
143 VSS
144 SYNCA O
145 WCA O$
146 F128A O$
147 F64A O$
148 EXTW O$
149 EXWI I$+
150 WCB I$
151 F256B I$
152 F64B I$
153 SYNCC I+
154 WCC I$+
155 F128C I$+
156 F64C I$+
157 VSS
158 DWCKI I$
159 DWCKO O$
160 VDD
I/O I: Input O: Output I/O: Bi-directional $: Clock signal OT: Tri-state output
+: Pull-up resistor built-in A: Analog terminal OD: Open drain
DC C: CMOS level T: TTL level
DC Level Function
T/C External RAM interface, data bus
T/C External RAM interface, data bus
Power supply +5V
C External RAM interface, address output (Unconnected)
C External RAM interface, address output (Unconnected)
C External RAM interface, address output (Unconnected)
C External RAM interface, address output (Unconnected)
C External RAM interface, address output
C External RAM interface, address output
GND
C External RAM interface, address output
C External RAM interface, address output
C External RAM interface, address output
C External RAM interface, address output
C External RAM interface, address output
C External RAM interface, address output
C External RAM interface, address output
GND
C External RAM interface, read strobe output
C External RAM interface, write strobe output
C External RAM interface, lower address strobe output
C External RAM interface column address strobe output
T SPD pin mute control input, muting provided at "1"
T Unconnected
Analog GND for PLL
Capacitance connection terminal for PLL
Analog power supply for PLL +5V
C Master clock, PLL lock detect output
T testing terminal (Unconnected)
T testing terminal (Unconnected)
GND
C 24.576MHz crystal oscillator connection terminal (input)
C 24.576MHz crystal oscillator connection terminal (output)
C Master clock, dividing clock output (256fs)
Power supply +5V
T Digital audio interface input A
T Digital audio interface input B
T Digital audio interface input C (Unconnected)
C Digital audio interface output
T Serial audio data input
T DIR5 interface, control data input
C DIR5 interface, control data output
C DIR5 interface, chip select output
C DIR5 interface, bit clock output
T DIR5 interface, interrupt input
T DIR5 interface, U-bit signal input
GND
C Master clock system, synchronous signal output
C Master clock system, word clock output (fs)
C Master clock system, dividing clock output (128fs)
C Master clock system, dividing clock output (64fs)
C Word clock output (fs)
T External word clock input (fs) (Unconnected)
T Digital input data system, word clock input (fs)
T Digital input data system, dividing clock input (256fs)
T Digital input data system, dividing clock input (64fs)
T (Unconnected)
T Mode switching, "1": normal operation, "0": PLL constant output mode
T (Unconnected)
T (Unconnected)
GND
T Drive word clock input (44.1kHz or 33.8688MHz)
C Drive word clock output (for charge couple)
Power supply +5V
CDR-HD1500
37