6-26.Schematic Diagram - Protect Section - Sony HCD-S300 Service Manual

IC204 IDT71V016S20PHAU
A4 1
ADDRESS BUFFER
A3 2
A2 3
ROW/COLUMN
DECODERS
A1 4
A0
5
CHIP ENABLE
CS 6
BUFFER
I/O 0
7
64K X 16
I/O 1 8
MEMORY
ARREY
I/O 2 9
10
I/O 3
11
I/O O
12
V
SS
I/O 4 13
14
I/O 5
I/O 6 15
8
LOW BYTE
I/O BUFFER DRIVERS
16
I/O 7
WE
17
WHITE ENABLE
BUFFER
A15 18
A14 19
A13 20
A12 21
NC 22
IC402, 403 MT48LC1M16A1TG
V
1
DD
DQ0 2
3
DQ1
DATA
OUTPUT
REGISTER
V Q 4
SS
DQ2 5
SENSE AMPLIFIERS
I/O GATING
DQ3 6
DOM MASK LOGIC
256
V Q
DD 7
256 (x16)
DQ4 8
BANK 0
MEMORY ARRAY
DQ5 9
(2.48 x 256 x 16)
2.048
10
V Q
SS
ROW
DECORDER
11
DQ6
12
DQ7
ROW-ADDRESS
LATCH
V Q 13
DD
DQML 14
WE# 15
CONTROL
LOGIC
CAS# 16
COMMAND
DECODER
RAS# 17
MODE
REGISTER
18
CS#
ROW-
ADDRESS
BA
19
MUX
20
A0
ADDRESS REGISTER
24
A3
V 25
DD
64
OUTPUT
ENABLE BUFFER
BYTE ENABLE
BUFFER
16
SENSE
AND
8
WRITE
HIGH BYTE
I/O BUFFER
DATA
INPUT
REGISTER
SENSE AMPLIFIERS
I/O GATING
DOM MASK LOGIC
COLUMN
256
DECODER
256 (x16)
COLUMN- BANK 1
ADDRESS MEMORY ARRAY
BUFFER (2.48 x 256 x 16)
2.048
BURST
ROW
COUNTER
DECORDER
COLUMN-
ROW-ADDRESS
ADDRESS
LATCH
LATCH
REFRESH
REFRESH
COUNTROLLER
COUNTER
IC304 MSM51V1816
44 A5
V 1
DD
43 A6
2
DQ1
A7
42
5
DQ4
41 OE
V 6
CC
40 BHE
7
DQ5
39
BLE
10
DQ8
38
I/O15
NC
11
37
I/O14
I/O
36 I/O13 CONT-
ROLLER
35 I/O 12
34 V
DD
NC 15
33
I/O O
16
NC
32 V 11
WE 17
31
I/O 10
RAS 18
GENERATOR
30 I/O 9
NC 19
29 I/O 8
NC 20
REFRESH
28 NC
CONTROL
27 A8
A0 21
26 A9
24
A3
25 A10
V 25
CC
24 A11
23 NC
V
50
SS
DQ15
49
48 DQ14
47 V Q
SS
46
V Q
DD
45
DQ12
44
V Q
DD
43 DQ11
42
DQ10
41 V Q
SS
40
DQ9
DQ8
39
38 V Q
DD
37 NC
36 DQMH
CLK
35
34 CKE
NC
33
A9
32
27
A4
26 V
SS
ON CHIP
V GENERATOR
BB
OUTPUT OUTPUT
BUFFERS BUFFERS
INPUT
BUFFERS BUFFERS
I/O
SELECTOR
I/O COLUMN SENSE
CONT- DECODERS AMPLIFIERS
ROLLER
TIMING
COLUMN INTERNAL
ADDRESS ADDRESS
CLOCK BUFFERS COUNTER
50 V
SS
DQ16
49
46
DQ13
45 47 V
SS
DQ12
44
INPUT
41
DQ9
40 NC
MEMORY
CELIS
WORD
DRIVERS
LOW
DECODERS
36
NC
35 LCAS
UCAS
34
OE
33
ROW
ADDRESS
BUFFERS
32
27
26 V
SS