Sony HD-FLX9W Service Manual page 92

HCD-FLX9W
Q Q
3 7 6 3 1 5 1 5 0
• IC Block Diagrams
– RF Board –
IC001 SP3723CAF0PM
64 63 62 61 60 59 58
INPUT
SEL ATT
4
INPUT
DVDRFP 1
MUX ATT AGC
BIAS
DVDRFN 2
2
2
INPUT
INPUT IMPEDANCE
IMPEDANCE SEL
SEL
+
CLAMP &
– ENVELOPE
BUFFER
2
LEVEL
SIGDET
DAC
COMPARATOR
A2 3
PHASE
– –
DETECTOR
B2 4
+
GCA EQ
+
C2 5
PHASE
DETECTOR
D2 6
3 3
T E
L 1 3 9 4 2 2 9 6 5 1 3
FROM FROM
VC
S-PORT S-PORT
CP 7
CN 8
A+D
D
D 9
+
GCA
+
C
C 10
FROM
+
GCA
B S-PORT
+
B 11
B+C
A
A
12 MUX GCA
3
CD/DVD
FROM
MUX
S-PORT
B+D
+
CD D 13
+
+
+
CD C 14
SUM
GCA
AMP
W/LPF
CD B 15
+
+
CD A 16
A+C
3
CD/DVD FROM
S-PORT
–
GCA
+
GCA
3 4
FROM FROM
S-PORT S-PORT
VCI FOR SERVO INPUT
VC = VPB/2
w w w APC SEL
DUAL APC
DVD/CD
LD H/L
FROM S-PORT
17 18 19 20 21 22 23 24 25 26 27
HCD-FLX9W
57 56 55 54 53 52 51 50
FAST ATTACK
OUTPUT
FULL WAVE AGC CHARGE
INHIBIT
RECTIFER PUMP
PROGRAMMABLE
FROM S-PORT
EQUALIZER
FILTER
DIFFERENTIATOR
AGCO
CONTROL
SERIAL
SIGNALS
PORT
+ TO EACH
REGISTER
BLOCK
–
V33 FOR
OUTPUT
3
BUFFER
LPF ATT
CE ATT
POL SEL
CEPOL
BUFFER
PI
FE
TE
CE
CONTROL
V25
V125
V25/3
TOPHOLD
–
OFFSET
GCA GCA
+ CANSEL
TOPHOLD
4
FROM
S-PORT
–
OFFSET
GCA LPF GCA GCA
+ CANSEL
4 5
FROM
S-PORT
OFFSET TE
GCA LPF GCA SUB GCA GCA
CANSEL RST
6 3
CP/CN
CEFDB FROM FROM
LOW
S-PORT S-PORT
IMPEDANCE
OFFSET
GCA LPF
CANSEL
5
FOR SERVO
FROM
OUTPUT
S-PORT
HOLDEN
V25/2
SEL
BCA
TOP
DET
HOLD
COMPA-
RATOR
–
2
FROM
+
GCA SEL
DAC
S-PORT
LINKEN
HYSTERESISTER
& OFFSET
FROM S-PORT
INPUT GAIN
INPUT
FROM S-PORT AGCO
IMPEDANCE
MIRR 2
2
FROM S-PORT
COMPARATOR SINK CURRENT
x a o
2
FROM S-PORT
PEAK/BOTTOM INPUT
INTERNAL
HOLD BUFFER
. i
FDGHG
28 29 30 31
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– MB Board –
IC215 SN74ALVCH16841DGGR
49
1OE 1 OE LE
AGC
1D1 2
HOLD
1D2 3
GND 4
1D3 5
1D4 6
VCC 7
LATCH
1D5 8
1D6 9
48 SDEN
47 SDATA
GND 10
46 SCLK
1D7
11
45 V33
1D8 12
1D9 13
1D10 14
44 LCP
43 LCN
2D1 15
2D2 16
2D3 17
MNTR
42 MNTR
GND 18
2D4 19
2D5 20
2D6
21
LATCH
Q Q
VCC 22
41 CE 3 7
2D7 23
2D8 24
GND
25
2D9 26
40 FE
2D10 27
2OE 28 OE LE
39 TE
38 PI
PH
37 V25
36 V125
35 TPH
DFT
34
33 LINK
BOTTOM
ENVELOPE
u 1 6 3
y
PH
MUX
32
92 92
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2 4
8 9 9
IC401 CXD9850Q
56 1LE
36 35 34 33 32 31
55 1Q1
1Q2
54
VDDL 37
53 GND
DSBCK 38
52 1Q3
DSIFL 39
PCM
51 1Q4
FIR FILTER
DSIFR 40 MUTE
&
DSICT 41
50 VCC
DOWN
DSISW 42
SAMPLING
49 1Q5
ROM
DSISL 43
UNIT
48 1Q6 24 bit
DSISR 44
720 word
GND
47
46 1Q7
45 1Q8
44 1Q9
43 1Q10 CLOCK
GENERATOR
DIRDSCK 45
&
SYNC 46
TIMING
42 2Q1
INIT 47
CONTROL
41 2Q2
40 2Q3 VSS 48
GND
39
38 2Q4
37 2Q5
1 2 3 4 5
36 2Q6
35 VCC
6 3 1 5 1 5 0 8 9
34 2Q7
2Q8
33
32 GND
31 2Q9
30 2Q10
29 2LE
m
c o
.
2
8 9 9
30 29 28 27 26 25
24 VSS
23 POFLR
INT/EXT
PCM
DATA 22 POCSW
I/F
SELECT
21 POSLR
20 PLRCK
INT/EXT
CLOCK 19 PBCK
SELECT
18 VDDH
17 MCKOUT
16 VSS
15 FMTPCM
14 DIRPCK
13 VDDL
TEST
CONTROL
6 7 8 9 10 11 12
2 4 9 8 2 9 9