Sony HD-FLX9W Service Manual page 116

HCD-FLX9W
QQ
3 7 63 1515 0
Pin No. Pin Name
VDDI
40
VSS
41
GP15
42
43 OE0
44 CS0
WE0
45
VDDE
46
47 WMD1
VSS
48
WMD0
49
PAGE2
50
51 VSS
PAGE1, PAGE0
52, 53
BOOT
54
BTACT
55
56 BST
MOD1
57
MOD0
58
EXLOCK
59
TE
VDDI
60
L 13942296513
61 VSS
A17, A16
62, 63
A15 to A13
64 to 66
GP10
67
DECODE
68
69 AUDIO
VDDI
70
VSS
71
D15 to D12
72 to 75
76 VDDE
D11 to D8
77 to 80
VSS
81
82 to 85 A9, A12 to A10
TDO
86
TMS
87
88 XTRST
TCK
89
TDI
90
VSS
91
www
A8 to A3
92 to 97
D7, D6
98, 99
VDDI
100
.
VSS
101
102 to 105 D5 to D2
106 VDDE
116
http://www.xiaoyu163.com
I/O
—
Power supply terminal (+3.3V)
—
Ground terminal
O
Column address strobe signal output terminal Not used
O Output enable signal output to the S-RAM
O
Chip select signal output to the S-RAM
O
Write enable signal output to the S-RAM
—
Power supply terminal (+3.3V)
I S-RAM wait mode setting terminal Fixed at "H" in this set
—
Ground terminal
I
S-RAM wait mode setting terminal Fixed at "L" in this set
O
Page selection signal output terminal Not used
— Ground terminal
O
Page selection signal output terminal Not used
I
Boot mode control signal input terminal Not used
O
Boot mode state display signal output terminal Not used
I Boot trap signal input from the digital audio interface receiver
I
PLL input frequency select terminal
I
Mode setting terminal
I
PLL lock error and data error flag input from the digital audio interface receiver
—
Power supply terminal (+3.3V)
— Ground terminal
O
Address signal output terminal Not used
O
Address signal output to the S-RAM
L/R sampling clock signal (44.1 kHz) output to the D/A, A/D converter and digital filter
O
Not used
O
Decode signal output to the system controller
I Bit 1 input terminal of channel status from the digital audio interface receiver
—
Power supply terminal (+3.3V)
—
Ground terminal
I/O
Two-way data bus with the S-RAM
— Power supply terminal (+3.3V)
I/O
Two-way data bus with the S-RAM
—
Ground terminal
O Address signal output to the S-RAM
O
Simple emulation data output terminal Not used
I
Simple emulation data input start/end detection signal input terminal Not used
I Simple emulation asychronous break input terminal Not used
I
Simple emulation clock signal input terminal Not used
I
Simple emulation data input terminal Not used
—
Ground terminal
O
Address signal output to the S-RAM
I/O
Two-way data bus with the S-RAM
x ao
y
—
Power supply terminal (+3.3V)
i
—
Ground terminal
I/O
Two-way data bus with the S-RAM
— Power supply terminal (+3.3V)
http://www.xiaoyu163.com
8
Description
"L": 384fs, "H": 256fs (fixed at "H" in this set)
"L": single chip mode, "H": use prohibition (fixed at "L" in this set)
Q Q
3 6 7 1 3
u163
.
2 9 9 4 2 8
1 5 0 5 8 2 9 9 4
m
co
9 9
2 8 9 9