Advanced Chipset Features; Dram Timing Selectable - Acorp 4S845A User Manual

Bhapter 1 Bhapter 1
Bhapter 1 Bhapter 1 Bhapter 1

2.4 Advanced Chipset Features

This section allows you to configure the system based on
the specific features of the installed chipset. This chipset
manages bus speeds and access to system memory resources,
such as DRAM and external cache. It also coordinates
communications of the PCI bus. It must be stated that these
items should never need to be altered. The default settings
have been chosen because they provide the best operating
conditions for your system. The only time you might
consider making any changes would be if you discovered that
data was lost while using your system.
◎ ◎ ◎ ◎ ◎ Figure 4. Advanced Chipset Features
CMOS Setup Utility-Copyright(C) 1984-2001 Award Software

DRAM Timing Selectable

DRAM Latency Time
Active to Precharge Delay
DRAM RAS# to CAS# Delay
DRAM RAS# Precharge
DRAM Data Integrity Mode
Memory Frequency For
DRAM Read Thermal Mgnt
System BIOS Cacheable
Video BIOS Cacheable
Video RAM Cacheable
Memory Hole At 15M-16M
Delayed Transaction
AGP Aperture Size (MB)
Delay Prior to Thermal
←→↑↓: Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit
F1:General Help
F7:Optimized Defaults
DRAM Timing Selectable
The DRAM timing is controlled by the DRAM Timing
Registers. The Timings programmed into this register are
dependent on the system design.
The Choices: By SPD(default), Manual.
Advanced Chipset Features
By SPD
1.5
7
3
3
Non-ECC
Auto
Enabled
Disabled
Disabled
Disabled
Disabled
Enabled
64
16 Min
F5:Previous Values F6:Fail-Safe Defaults
1-14 1-14 1-14
1-14 1-14
BIOS Settp BIOS Settp
BIOS Settp BIOS Settp BIOS Settp
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