Denon AVR-E400 Service Manual page 164

H27U1G8F2BTR-BC (HDMI : U2603)
1.2 PIN DESCRIPTION
H27U1G8F2BTR-BC Pin Function
Pin Name
IO0 ~ IO7
CLE
ALE
CE
WE
RE
WP
R/B
Vcc
Vss
NC
H27U1G8F2BTR-BC Block Diagram
A27 ~ A0
NOTE :
1. A 0.1uF capacitor should be connected between the Vcc Supply Voltage pin and the Vss Ground pin to decouple the
current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during
program and erase operations.
Rev 1.1 / Sep. 2009
DATA INPUTS/OUTPUTS
The IO pins allow to input command, address and data and to output data during read / program
operations. The inputs are latched on the rising edge of Write Enable (WE). The I/O buffer float to
High-Z when the device is deselected or the outputs are disabled.
COMMAND LATCH ENABLE
This input activates the latching of the IO inputs inside the Command Register on the Rising edge of
Write Enable (WE).
ADDRESS LATCH ENABLE
This input activates the latching of the IO inputs inside the Address Register on the Rising edge of
Write Enable (WE).
CHIP ENABLE
This input controls the selection of the device.
WRITE ENABLE
This input acts as clock to latch Command, Address and Data. The IO inputs are latched on the rise
edge of WE.
READ ENABLE
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is
valid tREA after the falling edge of RE which also increments the internal column address counter by
one.
WRITE PROTECT
The WP pin, when Low, provides an Hardware protection against undesired modify (program / erase)
operations.
READY BUSY
The Ready/Busy output is an Open Drain pin that signals the state of the memory.
SUPPLY VOLTAGE
The Vcc supplies the power for all the operations (Read, Write, Erase).
GROUND
NO CONNECTION
Table 2 : Pin Description
ADDRESS
REGISTER/
COUNTER
PROGRAM
ERASE
CONTROLLER
HV GENERATION
ALE
CLE
WE
CE COMMAND
INTERFACE
WP
LOGIC
RE
COMMAND
REGISTER
DATA
REGISTER
Figure 4 : Block Diagram
H27U1G8F2B Series
1 Gbit (128 M x 8 bit) NAND Flash
Description
H27U1G8F2B Series
1 Gbit (128 M x 8 bit) NAND Flash
1024 Mbit + 32 Mbit
NAND Flash
MEMORY ARRAY
PAGE BUFFER
Y DECODER
BUFFERS
IO
164
1
1
X
D
E
C
O
D
E
R
6