3. H/W Circuit Description
3.3.2. Audio Signal Processing & Interface
Audio signal processing is divided Uplink path and downlink path.
The uplink path amplifies the audio signal from MIC and converts this analog signal to digital signal
and then transmit it to DBB Chip. This transmitted signal is reformed to fit in GSM Frame format and
delivered to RF Chip. MICBIAS is 2.0Vlevel.
The downlink path amplifies the signal from DBB chip and outputs it to Receiver (or Speaker).
Figure 12. Audio Interface Block Diagram
3.3.3. Audio uplink processing
The microphone is soldered to the main PCB. The uplink signal is passed to MICIP and MICIN pins of
IOTA.
The MICBIAS voltage is supplied from IOTA(dedicated mode only). When the headset is inserted,
ADC value of HOOK_DETECT(IO6) terminal is between 20 to 150 (decimal value). On detecting this,
Calypso makes IOTA switches the MIC amplifier path from main to auxiliary.
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