Digital Baseband(Dbb) Processor; General Description - LG L1150 Service Manual

3. H/W Circuit Description

3.2. Digital Baseband(DBB) Processor

O Circuito Receptor, localizado no CX74017, contém todos os circuitos completamente ativados,
corrente total do receptor com exceção dos filtros RF SAW discretos da extremidade frontal. O sinal
filtrado e amplificado é convertido em um mixer RF para saída banda base. O caminho de recepção é
fornecido por um filtro interno de canal.
Figure 7. Top level block diagram of the Calypso G2(HERCROM400G2)

3.2.1. General Description

CALYPSO is a chip implementing the digital base-band processes of a GSM/GPRS mobile phone.
This chip combines a DSP sub-chip (LEAD2 CPU) with its program and data memories, a Micro- -
Controller core with emulation facilities (ARM7TDMIE), internal 8Kb of Boot ROM memory, 4M bit
SRAM memory, a clock squarer cell, several compiled single-port or 2-ports RAM and CMOS gates.
The chip will fully support the Full-Rate, Enhanced Full-Rate and Half-Rate speech coding.
CALYPSO implements all features for the structural test of the logic (full-SCAN, BIST, PMT, JTAG
boundary-SCAN).
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