ECS A960M-M3 Manual page 47

Memory Control
Scroll to this item and press <Enter> to view the following screen.
Aptio Setup Utility - Copyright (C) 2011 American Megatrends, Inc.
Main Advanced Chipset
Memory Control
Memory Clock DCT0 is :
Memory Clock DCT1 is :
Command Rate
Memory Clock Mode
Memory Timing Mode
CAS Latency
RAS to CAS Delay
Row Precharge Time
RAS Active Time
Row Cycle Time
RAS to RAS Delay
Read CAS to Precharge Time
Version 2.14.1219. Copyright (C) 2011, American Megatrends, Inc.
Memory Clock DCT0 is DDR-1333/667Mhz
This item shows current memory clock of DCTO.
Memory Clock DCT1 is None
This item shows current memory clock of DCT1.
Command Rate (Auto)
This item is used to set the Command Rate.
Memory Clock Mode (Auto)
This item is used to set the memory clock Mode.
Memory Timing Mode (Auto)
This item is used to set the memory Timing Mode.
CAS Latency (9)
This item determines the operation of DDR SDRAM memory CAS (column address
strobe). It is recommanded that you leave this item at the default value. The 2Tsetting
requires faster memory that specifically supports this mode.
RAS to CAS Delay (9)
This item specifies the RAS# to CAS# delay to Rd/Wr command to the same bank.
Row Precharge Time (9)
This item specifies Row precharge to Active or Auto-Refresh of the same bank.
RAS Active Time (24)
This item specifies the RAS# active time.
Row Cycle Time (33)
Use this item to specify the Row Cycle Time.
RAS to CAS Delay (4)
This item specifies the active-to-active delay of different banks.
Read CAS to Precharge Time (5)
Read to Precharge Delay, range from 4 to 15.
A960M-M3 USER MANUAL
M.I.B.III Boot Security
(DDR-1333/667Mhz)
None
[Auto]
[Auto]
[Auto]
9
9
9
24
33
4
5
Exit
Slow Access Mode
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Enter/Dbl Click : Select
+/- : Change Opt.
F1: General Help
F2: Previous Values
F3: Optimized Defaults
F4: Save & Exit
ESC/Right Click: Exit
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