Pin Description - Denon AVR-1912E3 Service Manual

Integrated network av receiver
Table of Contents

Advertisement

W9864G6JH-6 Pin description

5. PIN DESCRIPTION

PIN NUMBER
24, 25, 26, 27, 60, 61, 62,
63, 64, 65, 66
22, 23
2, 4, 5, 7, 8, 10, 11, 13, 31,
33, 34, 36, 37, 39, 40, 42,
45, 47, 48, 50, 51, 53, 54,
56, 74, 76, 77, 79, 80, 82,
83, 85
20
19
18
17
16, 28, 59, 71
68
67
1, 15, 29, 43
44, 58, 72, 86
3, 9, 35, 41, 49, 55, 75, 81
6, 12, 32, 38, 46, 52, 78, 84
14, 21, 30, 57, 69, 70, 73
PIN NAME
FUNCTION
A0−A10
Address
BS0, BS1
Bank Select
Data
DQ0−DQ31
Input/ Output
Chip Select
CS
Row Address
RAS
Strobe
Column Address
CAS
Strobe
Write Enable
WE
Input/Output
DQM0 − DQM3
Mask
CLK
Clock Inputs
CKE
Clock Enable
V
Power
DD
V
Ground
SS
Power for I/O
V
DDQ
Buffer
Ground for I/O
V
SSQ
Buffer
NC
No Connection No connection.
- 5 -
DESCRIPTION
Multiplexed pins for row and column address.
Row address: A0−A10. Column address: A0−A7.
A10 is sampled during a precharge command to
determine if all banks are to be precharged or
bank selected by BS0, BS1.
Select bank to activate during row address latch
time, or bank to read/write during address latch
time.
Multiplexed pins for data output and input.
Disable or enable the command decoder. When
command decoder is disabled, new command is
ignored and previous operation continues.
Command input. When sampled at the rising
edge of the clock RAS , CAS and WE
define the operation to be executed.
Referred to RAS
Referred to RAS
The output buffer is placed at Hi-Z (with latency
of 2) when DQM is sampled high in read cycle.
In write cycle, sampling DQM high will block the
write operation with zero latency.
System clock used to sample inputs on the rising
edge of clock.
CKE controls the clock activation and
deactivation. When CKE is low, Power Down
mode, Suspend mode, or Self Refresh mode is
entered.
Power for input buffers and logic circuit inside
DRAM.
Ground for input buffers and logic circuit inside
DRAM.
Separated power from VDD, to improve DQ
noise immunity.
Separated ground from VSS, to improve DQ
noise immunity.
Publication Release Date: Aug. 28, 2009
157
W9864G2IH
Revision A03

Hide quick links:

Advertisement

Table of Contents
loading

Table of Contents