Pin Function Description; Pin Configuration; Input Function - Denon AVR-S730H Service Manual

MX25L6406EM2I-12G (DIGITAL_DSP : IC782)
Block diagram
M12L64164A-5TG2Y (DIGITAL_DSP : IC784)
Vdd
DQ0
VddQ
DQ1
DQ2
VssQ
DQ3
DQ4
VddQ
DQ5
DQ6
VssQ
DQ7
Vdd
LDQM
/WE
/CAS
/RAS
/CS
BA0
BA1
A10(AP)
A0
A1
A2
A3
Vdd
CLK : Master Clock
CKE : Clock Enable
/CS : Chip Select
ESMT
/RAS : Row Address Strobe
/CAS : Column Address Strobe
/WE : Write Enable
DQ0-15 : Data I/O
Block diagram
FUNCTIONAL BLOCK DIAGRAM
CLK
Clock
Generator
CKE
Address
Revision 1.0
Mode
Register
CS
RAS
CAS
WE

PIN FUNCTION DESCRIPTION

PIN NAME
CLK System Clock
Chip Select
CS
CKE Clock Enable
A0 ~ A11 Address
BA1 , BA0 Bank Select Address
Row Address Strobe
RAS
51
Column Address Strobe
CAS

PIN CONFIGURATION

(TOP VIEW)
Vss
1 54
DQ15
2 53
VssQ
3 52
DQ14
4 51
DQ13
5 50
VddQ
6 49
DQ12
7 48
DQ11
8 47
VssQ
9 46
DQ10
10 45
DQ9
11 44
VddQ
12 43
DQ8
13 42
Vss
14 41
NC
15 40
UDQM
16 39
CLK
17 38
CKE
18 37
NC
19 36
A11
20 35
A9
21 34
A8
22 33
A7
23 32
A6
24 31
A5
25 30
A4
26 29
Vss
27 28
U,LDQM : Output Disable / Write Mask
A0-11 : Address Input
BA0,1 : Bank Address
Vdd : Power Supply
M12L64164A (2Y)
VddQ : Power Supply for Output
Vss : Ground
VssQ : Ground for Output
Bank D
Bank C
Bank B
Row
Address
Buffer Page 2/39
Dec., 2012
Bank A
&
Refresh
Counter
Sense Amplifier
Column
Column Decoder
Address
Buffer
&
Refresh
Counter
Data Control Circuit

INPUT FUNCTION

Active on the positive going edge to sample all inputs
Disables or enables device operation by masking or enabling all
inputs except CLK , CKE and L(U)DQM
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior new command.
Disable input buffers for power down in standby.
Row / column address are multiplexed on the same pins.
Row address : RA0~RA11, column address : CA0~CA7
Selects bank to be activated during row address latch time.
Selects bank for read / write during column address latch time.
Latches row addresses on the positive going edge of the CLK with
RAS low.
Enables row access & precharge.
Latches column address on the positive going edge of the CLK with
CAS low.
Enables column access.
L(U)DQM
DQ