Toshiba TDP-D1 Service Manual page 90

In this figure, HSync and VSync are sent to the ImageProcessor. These signals must be buffered
to 3.3V before goingto the ImageProcessor. The feedback signal (GFBK) is the HSync signal created
by the PLL. After the PLL has locked on, GFBK is virtually identical to HSync, except for a phase
delay. The ImageProcessor requires both of these HSync signals for two purposes:
  H Sync is not synchronous to GCLK, so GFBK is needed to indicate the start of active data.
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  G FBK is not stable until the PLL is locked, so GHS is required to measure the incoming signal so
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that the PLL can be initialized.
The Coast signal is sent to the PLL to tell it to free-run and ignore edges on the reference input. This
is used to ignore false transitions on HSync during vertical blanking that are often present in
composite sync inputs.
Video Port (VPort)
Figure 5 illustrates a sample circuit for the Video Decoder interface to the Pixelworks
ImageProcessor.
The Video Port can receive data in 8-bit CCIR656, 16-bit YUV, 24-bit YUV, or 24-bit RGB
formats. For YUV input modes, YUV to RGB conversion is performed in the Color Space Converter
in the ImageProcessor. In addition, the data to the Video Port can be qualified with a VPEN input.
This allows the clock to be run at a frequency faster than the data.
Figure 5. Sample VPort Circuit
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