Toshiba TDP-D1 Service Manual page 82

This section provides design guidelines for the RGB Analog interface, and describes:
  I nput Signals
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  S ync on Green (SOG)
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  P ower
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  C locks and Phase Lock Loop (PLL)
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  L ayout
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Input Signals
Care must be taken to minimize input capacitance while reducing sensitivity to noise on the
input. These are opposing themes when attempting to customize the input for specific performance.
To attempt to satisfy these goals, consider the following guidelines:
  K eep the input termination impedance 75
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do so, use an inductance to balance the board stray capacitance. This reduces unwanted termination
reflections at the frequencies of interest.
  T he actual termination resistor needs to have its ground return point as close to the 15

connector as possible.
  A fter this initial termination, th
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amount of stray capacitance. This stray capacitance comes primarily from the ESD protection
devices and the input circuit to the display processor. This capacitance can again be balanced out
with the proper amount of series inductance prior to the ESD protection device.
  K eep signal trace width as narrow as possible for these analog signals; the reason for this is that
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the wider the trace, the higher the stay capacitance. Also, after the initial 75
subsystem needs to be considered high impedance.
 a t frequencies up to twice the display design goal. To
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e circuit board appears as a high-impedance subsystem with a large
-pin
 t ermination, the
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