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iSBC 432/100
Principles of Operation
(G) SINGLE-BYTE WRITE TRANSFER, 16-BIT MODE
DATs-FI
(H) DOUBLE-BYTE READ/WRITE TRANSFER, 16-BIT MODE
Figure 4-5. iSBC 432/100™ Data Transfer Routing to/from the Multibus™ Bus (Cont'd.)
rns20-~o
4.7 MULTIBUS INTERFACE
The iSBC 432/100 board is completely Multibus
compatible and supports both 8-bit and 16-bit opera-
tions. The Multibus interface includes an 8288/8289
controller/arbiter pair that allows the iSBC 432/100
board to function as a Multibus master. Also
included in the Multibus interface are address/data
bus transceivers and latches and an 1/0 command
decoder (discussed in paragraph 4-18). All 1/0 ports
are directly accessible from the Multibus by any
Multibus master.
4.8 INTERVAL TIMER
The 8253 PIT provides three 16-bit timers used
on-board for serial 1/0 timing and for process
timing. Counters 0 and 1 are cascaded to provide the
process clock (PCLK) signal. Counter 2 generates a
programmable baud rate for the 8251A serial 1/0
port. Baud rates from 110 to 19 .2K are easily
generated as discussed in paragraph 3-20 and
table 3-2.
4.9 SERIAL I/O
The 8251A USART provides an RS-232-C compat-
ible serial synchronous or asynchronous data link for
CRT terminal operation. Character size, parity bits,
stop bits, and baud rates are all programmable as
discussed in paragraph
~-5.
4.10 PARALLEL I/O
Four parallel 1/0 ports are contained on the iSBC
432/ 100 board to support processor control and
status reporting functions. An 8-bit offset register
(write-only), used in addressing calculations (refer to
paragraphs 4-5 and 4-18), may be set from the
Multibus bus to translate processor addresses into
Multibus addresses. A second write-only 1/0 port
controls processor initialization and allows another
Multibus master to start, stop, and alarm the iSBC
432/100 processor (see paragraph 3-23).
4-7
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